Edwin Thaller

According to our database, Edwin Thaller authored at least 5 papers between 2004 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS.

Edwin Thaller, Run Levinger, Evgeny Shumaker, Aryeh Farber, Sergey Bershansky, Nir Geron, Ashoke Ravi, Rotem Banin, Jasmin Kadry, Gil Horovitz, Christian Krassnitzer, Christoph Duller, Patrick Torta, Mark Elzinga, Kamran Azadet

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2017

13.9 A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE.

Antonio Passamani, Davide Ponton, Edwin Thaller, Gerhard Knoblinger, Andrea Neviani, Andrea Bevilacqua

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

Digital compensation of DC-DC converter voltage ripple for Switched-Capacitor Power Amplifiers.

Stefan Trampitsch, Daniel Gruber, Michael Lunglmayr, Edwin Thaller, Mario Huemer

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

2005

A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS.

Nicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi

IEEE J. Solid State Circuits, 2005

2004

A low jitter triple-band digital LC PLL in 130nm CMOS.

Nicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi

Proceedings of the 33rd European Solid-State Circuits Conference, 2004