Nicola Da Dalt

According to our database1, Nicola Da Dalt authored at least 22 papers between 2004 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Design and implementation of switched coil LC-VCOs in the GHz range using the self-inductance technique.
Int. J. Circuit Theory Appl., 2015

F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
An Analysis of Phase Noise in Realigned VCOs.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

F6: Energy-efficient I/O design for next-generation systems.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture.
IEEE J. Solid State Circuits, 2013

A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

An all-digital PLL using random modulation for SSC generation in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

ES3: High-speed communications on 4 wheels: What's in your next car?
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011
Jitter Noise of Sampled Multitone Signals.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

2010
A 0.06 mm <sup>2</sup> 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010

A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 4.1 to 5.1 GHz 430 μA injection-locked frequency divider by 7 in 65 nm CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

2006
Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

A 10b 10GHz digitlly controlled LC oscillator in 65nm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

2004
Effect of jitter on asynchronous sampling with finite number of samples.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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