Ashoke Ravi
Orcid: 0000-0001-8302-622X
According to our database1,
Ashoke Ravi
authored at least 42 papers
between 2004 and 2023.
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Bibliography
2023
A 1.8W High-Frequency SIMO Converter Featuring Digital Sensor-Less Computational Zero-Current Operation and Non-Linear Duty-Boost.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 16nm, +28dBm Dual-Band All-Digital Polar Transmitter Based on 4-core Digital PA for Wi-Fi6E Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
A Cellular Multiband DTC-Based Digital Polar Transmitter With -153-dBc/Hz Noise in 14-nm FinFET.
IEEE J. Solid State Circuits, 2020
A Fully Integrated 27-dBm Dual-Band All-Digital Polar Transmitter Supporting 160 MHz for Wi-Fi 6 Applications.
IEEE J. Solid State Circuits, 2020
10.5 A Fully Integrated 27dBm Dual-Band All-Digital Polar Transmitter Supporting 160MHz for WiFi 6 Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A Cellular Multiband DTC-Based Digital Polar Transmitter With -153 dBc/Hz Noise in 14-nm FinFET.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
802.11g/n Compliant Fully Integrated Wake-Up Receiver With -72-dBm Sensitivity in 14-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2017
13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
2016
A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS.
IEEE J. Solid State Circuits, 2016
2.9 A 2GHz 244fs-resolution 1.2ps-Peak-INL edge-interpolator-based digital-to-time converter in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
Proceedings of the 2015 IEEE International Conference on RFID, 2015
2013
IEEE J. Solid State Circuits, 2013
A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique.
IEEE J. Solid State Circuits, 2013
2012
A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement.
IEEE J. Solid State Circuits, 2012
A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS.
IEEE J. Solid State Circuits, 2012
A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A digital fractional-N PLL with a 3mW 0.004mm<sup>2</sup> 6-bit PVT and mismatch insensitive TDC.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application.
IEEE J. Solid State Circuits, 2011
A 31.5dBm outphasing class-D power amplifier in 45nm CMOS with back-off efficiency enhancement by dynamic power control.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
2010
A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving.
IEEE J. Solid State Circuits, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
IEEE J. Solid State Circuits, 2009
A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving.
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
A 28.6dBm 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A 3.6GHz, 16mW ΣΔ DAC for a 802.11n / 802.16e transmitter with 30dB digital power control in 90nm CMOS.
Proceedings of the ESSCIRC 2008, 2008
Proceedings of the ESSCIRC 2008, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2006
A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process.
IEEE J. Solid State Circuits, 2006
A 5-GHz 108-Mb/s 2 $\times$2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm ${\rm P}_{\rm 1dB}$ Power Amplifiers in 90-nm CMOS.
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3<sup>rd</sup> order, 3/5-bit IIR and 3<sup>rd</sup> order 3-bit-FIR noise shapers in 90nm CMOS.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004