Eladio Gutiérrez

Sonia Gonzalez-Navarro

J. Comput. Sci., 2022

Accelerating Time Series Analysis via Processing using Non-Volatile Memories.

[BibT_eX]

[DOI]

CoRR, 2022

Exploiting Vector Extennsions to Accelerate Time Series Analysis.

[BibT_eX]

[DOI]

Proceedings of the 30th Euromicro International Conference on Parallel, 2022

Exploiting Near-Data Processing to Accelerate Time Series Analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

2021

An Abstract Machine Approach to Preserving Digital Information.

[BibT_eX]

[DOI]

IEEE Access, 2021

2020

Energy-Efficient Time Series Analysis Using Transprecision Computing.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Symposium on Computer Architecture and High Performance Computing, 2020

NATSA: A Near-Data Processing Accelerator for Time Series Analysis.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019

Accelerating time series motif discovery in the Intel Xeon Phi KNL processor.

[BibT_eX]

[DOI]

J. Supercomput., 2019

Improving hardware transactional memory parallelization of computational geometry algorithms using privatizing transactions.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2019

2018

Privatizing transactions for Lee's algorithm in commercial hardware transactional memory.

[BibT_eX]

[DOI]

J. Supercomput., 2018

TMbarrier: Speculative Barriers Using Hardware Transactional Memory.

[BibT_eX]

[DOI]

Manuel Pedrero

Proceedings of the 26th Euromicro International Conference on Parallel, 2018

2017

Lazy Irrevocability for Best-Effort Transactional Memory Systems.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2017

Leveraging irrevocability to deal with signature saturation in hardware transactional memory.

[BibT_eX]

[DOI]

J. Supercomput., 2017

Enhancing scalability in best-effort hardware transactional memory systems.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2017

ReduxSTM: Optimizing STM designs for Irregular Applications.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2017

2016

A comparative analysis of STM approaches to reduction operations in irregular applications.

[BibT_eX]

[DOI]

J. Comput. Sci., 2016

Insights into the Fallback Path of Best-Effort Hardware Transactional Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2016: Parallel Processing, 2016

2015

Improving Transactional Memory Performance for Irregular Applications.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computational Science, 2015

Conflict Detection in Hardware Transactional Memory.

[BibT_eX]

[DOI]

Proceedings of the Transactional Memory. Foundations, Algorithms, Tools, and Applications, 2015

2014

Effective Transactional Memory Execution Management for Improved Concurrency.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2014

Improving Signature Behavior by Irrevocability in Transactional Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Scalability Analysis of Signatures in Transactional Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

2013

Hardware Signature Designs to Deal with Asymmetry in Transactional Data Sets.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2013

LS-Sig: Locality-Sensitive Signatures for Transactional Memory.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

E-assessment of Matlab assignments in Moodle: Application to an introductory programming course for engineers.

[BibT_eX]

[DOI]

Comput. Appl. Eng. Educ., 2013

Dealing with Reduction Operations Using Transactional Memory.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

An Experience of e-Assessment in an Introductory Course on Computer Organization.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computational Science, 2013

Parallelizing the Sparse Matrix Transposition: Reducing the Programmer Effort Using Transactional Memory.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computational Science, 2013

Exploring Irregular Reduction Support in Transactional Memory.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

2011

Use of a New Moodle Module for Improving the Teaching of a Basic Course on Computer Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Educ., 2011

Multiset signatures for transactional memory.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Unified Locality-Sensitive Signatures for Transactional Memory.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

2010

Quantum computer simulation using the CUDA programming model.

[BibT_eX]

[DOI]

Comput. Phys. Commun., 2010

A new Moodle module supporting automatic verification of VHDL-based assignments.

[BibT_eX]

[DOI]

Comput. Educ., 2010

Interval Filter: A Locality-Aware Alternative to Bloom Filters for Hardware Membership Queries by Interval Classification.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Data Engineering and Automated Learning, 2010

2009

Experiences with Mapping Non-linear Memory Access Patterns into GPUs.

[BibT_eX]

[DOI]

Proceedings of the Computational Science, 2009

Improving Signatures by Locality Exploitation for Transactional Memory.

[BibT_eX]

[DOI]

Proceedings of the PACT 2009, 2009

2008

An analytical model of locality-based parallel irregular reductions.

[BibT_eX]

[DOI]

Parallel Comput., 2008

Memory Locality Exploitation Strategies for FFT on the CUDA Architecture.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing for Computational Science, 2008

Development of a new MOODLE module for a basic course on computer architecture.

[BibT_eX]

[DOI]

Proceedings of the 13th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, 2008

Parallel Quantum Computer Simulation on the CUDA Architecture.

[BibT_eX]

[DOI]

Proceedings of the Computational Science, 2008

2005

On the parallelization of irregular and dynamic programs.

[BibT_eX]

[DOI]

Parallel Comput., 2005

Parallel techniques in irregular codes: cloth simulation as case of study.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2005

2004

Parallelization issues of a code for physically-based simulation of fabrics.

[BibT_eX]

[DOI]

Comput. Phys. Commun., 2004

Data partitioning-based parallel irregular reductions.

[BibT_eX]

[DOI]

Concurr. Comput. Pract. Exp., 2004

Optimization Techniques for Irregular and Pointer-Based Programs.

[BibT_eX]

[DOI]

Rafael Asenjo

Francisco Corbera

M. Angeles Gonzales Navarro

Proceedings of the 12th Euromicro Workshop on Parallel, 2004

2003

Optimization techniques for parallel irregular reductions.

[BibT_eX]

[DOI]

J. Syst. Archit., 2003

2002

On Improving the Performance of Data Partitioning Oriented Parallel Irregular Reductions.

[BibT_eX]

[DOI]

Proceedings of the 10th Euromicro Workshop on Parallel, 2002

2001

Improving parallel irregular reductions using partial array expansion.

[BibT_eX]

[DOI]

Proceedings of the 2001 ACM/IEEE conference on Supercomputing, 2001

Balanced, Locality-Based Parallel Irregular Reductions.

[BibT_eX]

[DOI]

Proceedings of the Languages and Compilers for Parallel Computing, 2001

2000

Automatic parallelization of irregular applications.

[BibT_eX]

[DOI]

Parallel Comput., 2000

A compiler method for the parallel execution of irregular reductions in scalable shared memory multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 14th international conference on Supercomputing, 2000

1999

On Automatic Parallelization of Irregular Reductions on Scalable Shared Memory Systems.

[BibT_eX]

[DOI]