Sonia Gonzalez-Navarro

Orcid: 0000-0002-5636-7042

According to our database1, Sonia Gonzalez-Navarro authored at least 20 papers between 2007 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2022
TraTSA: A Transprecision Framework for Efficient Time Series Analysis.
J. Comput. Sci., 2022

2021
Enabling fast and energy-efficient FM-index exact matching using processing-near-memory.
J. Supercomput., 2021

Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures.
IEEE Trans. Computers, 2021

2020
Accelerating Sequence Alignments Based on FM-Index Using the Intel KNL Processor.
IEEE ACM Trans. Comput. Biol. Bioinform., 2020

New Results on Non-Normalized Floating-Point Formats.
IEEE Trans. Computers, 2020

Floating-Point Fused Multiply-Add under HUB Format.
Proceedings of the 27th IEEE Symposium on Computer Arithmetic, 2020

2019
Fast HUB Floating-Point Adder for FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding.
Proceedings of the Data Compression Conference, 2019

2018
Unbiased Rounding for HUB Floating-Point Addition.
IEEE Trans. Computers, 2018

2017
Normalizing or Not Normalizing? An Open Question for Floating-Point Arithmetic in Embedded Systems.
Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017

2016
Decimal Multiformat Online Addition.
IEEE Trans. Computers, 2016

2013
Binary Integer Decimal-Based Floating-Point Multiplication.
IEEE Trans. Computers, 2013

2012
A study of decimal left shifters for binary numbers.
Inf. Comput., 2012

On-line Decimal Adder with RBCD Representation.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

Decimal online multioperand addition.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
Hardware Designs for Binary Integer Decimal-Based Rounding.
IEEE Trans. Computers, 2011

2009
Analytical Model of Patching and Load Sharing in a Distributed VoD System.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

A Combined Decimal and Binary Floating-Point Multiplier.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2007
Hardware design of a Binary Integer Decimal-based floating-point adder.
Proceedings of the 25th International Conference on Computer Design, 2007

Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007


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