Olivier Billoint

According to our database1, Olivier Billoint authored at least 32 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Memory Window in Si: HfO2 FeRAM arrays: Performance Improvement and Extrapolation at Advanced Nodes.
Proceedings of the IEEE International Memory Workshop, 2023

2021
Area and Cost Analysis of the Mixed Signal Circuits in a Novel Monolithic 3D Process.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021


2020
M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018
A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Cell-on-Buffer: New design approach for high-performance and low-power monolithic 3D integrated circuits.
Microelectron. J., 2017

Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2016


Impact of intermediate BEOL technology on standard cell performances of 3D VLSI.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

From 2D to monolithic 3D predictive design platform: An innovative migration methodology for benchmark purpose.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking.
IEEE J. Solid State Circuits, 2015

Compact interconnect approach for networks of neural cliques using 3D technology.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

An Unbalanced Area Ratio Study for High Performance Monolithic 3D Integrated Circuits.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

UTBB FDSOI technology flexibility for ultra low power internet-of-things applications.
Proceedings of the 45th European Solid State Device Research Conference, 2015

A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Intermediate BEOL process influence on power and performance for 3DVLSI.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
3D technologies for reconfigurable architectures.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014


A high-level design rule library addressing CMOS and heterogeneous technologies.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

3DCoB: A new design approach for Monolithic 3D Integrated circuits.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design?
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013


Distributed clock generator for synchronous SoC using ADPLL network.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013


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