Gregory di Pendina

Orcid: 0000-0002-7698-1971

According to our database1, Gregory di Pendina authored at least 26 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
On Using Cell-Aware Methodology for SRAM Bit Cell Testing.
Proceedings of the IEEE European Test Symposium, 2023

2022
MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the Edge.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

CMOS/STT-MRAM Based Ascon LWC: a Power Efficient Hardware Implementation.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2020
A Universal Spintronic Technology based on Multifunctional Standardized Stack.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power Microcontrollers.
IEEE Access, 2019

Light-Weight Cipher Based on Hybrid CMOS/STT-MRAM: Power/Area Analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Dual Detection of Heating and Photocurrent attacks (DDHP) Sensor using Hybrid CMOS/STT-MRAM.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2018
From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

High density SOT-MRAM memory array based on a single transistor.
Proceedings of the Non-Volatile Memory Technology Symposium, 2018

Impact of a Laser Pulse on a STT-MRAM Bitcell: Security and Reliability Issues.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

MRAM: from STT to SOT, for security and memory.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Using multifunctional standardized stack as universal spintronic technology for IoT.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
High speed and high-area efficiency non-volatile look-up table design based on magnetic tunnel junction.
Proceedings of the 17th Non-Volatile Memory Technology Symposium, 2017

GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016
Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing.
IEEE Trans. Multi Scale Comput. Syst., 2016

Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories.
ACM J. Emerg. Technol. Comput. Syst., 2016

2015
Radiative Effects on MRAM-Based Non-Volatile Elementary Structures.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Ultra-low power volatile and non-volatile asynchronous circuits using back-biasing.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014
InMRAM: Introductory course on Magnetic Random Access Memories for microelectronics students and engineers.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

Magnetic memories: From DRAM replacement to ultra low power logic chips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Hybrid CMOS/magnetic Process Design Kit and SOT-based non-volatile standard cell architectures.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Non-volatile FPGAs based on spintronic devices.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2011
Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Hybrid CMOS/Magnetic Process Design Kit and application to the design of high-performances non-volatile logic circuits.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2009
Infrastructures for Education, Research and Industry in Microelectronics A Look Worldwide and a Look at India.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009


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