Edith Beigné
Orcid: 0000-0001-6350-1054
According to our database1,
Edith Beigné
authored at least 100 papers
between 2005 and 2024.
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Collaborative distances:
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Bibliography
2024
A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications.
IEEE Micro, 2024
11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A prototype 5nm custom sensor SoC for Augmented Reality/Virtual Reality targeting Smartglasses with embedded computer vision, audio, security and ML.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the 28th IEEE International Symposium on Asynchronous Circuits and Systems, 2023
2022
Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications.
IEEE Micro, 2022
Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
2020
SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing.
IEEE J. Solid State Circuits, 2019
ACM J. Emerg. Technol. Comput. Syst., 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning.
Proceedings of the 24th IEEE European Test Symposium, 2019
A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Misalignment Analysis and Electrical Performance of High Density 3D-IC interconnects.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
2018
A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Session 18 overview: Adaptive circuits and digital regulators: Digital circuit techniques subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 2.5μW 0.0067mm<sup>2</sup> automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V VDD range.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Some Local Stability Properties of an Autonomous Long Short-Term Memory Neural Network Model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
BISTs for post-bond test and electrical analysis of high density 3D interconnect defects.
Proceedings of the 23rd IEEE European Test Symposium, 2018
FDSOI circuit design for high energy efficiency: Wide operating range and ULP applications - a 7-year experience.
Proceedings of the 48th European Solid-State Device Research Conference, 2018
2017
AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017
High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Micro, 2017
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.
IEEE J. Solid State Circuits, 2017
J. Low Power Electron., 2017
Architecture exploration of a fixed point computation unit using precise timing spiking neurons.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
Innovative structures to test bonding alignment and characterize high density interconnects in 3D-IC.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
A 128x128, 34μm pitch, 8.9mW, 190mK NETD, TECless Uncooled IR bolometer image sensor with column-wise processing.
Proceedings of the Image Sensors and Imaging Systems 2017, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications.
Proceedings of the 17th Latin-American Test Symposium, 2016
8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications.
Proceedings of the International Conference on IC Design and Technology, 2016
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016
2015
IEEE J. Solid State Circuits, 2015
A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems.
ACM J. Emerg. Technol. Comput. Syst., 2015
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Power gain estimation of an event-driven wake-up controller dedicated to WSN's microcontroller.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
UTBB FDSOI technology flexibility for ultra low power internet-of-things applications.
Proceedings of the 45th European Solid State Device Research Conference, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015
2014
Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC.
IEEE J. Solid State Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, Dallas, TX, USA, October 29, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC.
Proceedings of the ESSCIRC 2013, 2013
A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Automatic Leakage Control for Wide Range Performance QDI Asynchronous Circuits in FD-SOI Technology.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013
Proceedings of the American Control Conference, 2013
2012
Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations.
J. Low Power Electron., 2012
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
Local Condition Monitoring in integrated circuits using a set of Kolmogorov-Smirnov tests.
Proceedings of the IEEE International Conference on Control Applications, 2012
2011
Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization.
Microelectron. J., 2011
On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling.
J. Low Power Electron., 2011
Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures.
J. Low Power Electron., 2011
Bringing Robustness and Power Efficiency to Autonomous Energy-Harvesting Microsystems.
IEEE Des. Test Comput., 2011
Low-Cost Dynamic Voltage and Frequency Management Based upon Robust Control Techniques under Thermal Constraints.
Proceedings of the Formal Methods for Components and Objects, 10th International Symposium, 2011
2010
An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process.
J. Low Power Electron., 2010
On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Bringing Robustness and Power Efficiency to Autonomous Energy Harvesting Microsystems.
Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE J. Solid State Circuits, 2009
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
2008
Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability.
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs.
Proceedings of the ESSCIRC 2008, 2008
Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008
2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006
2005
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework.
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005