Elisardo Antelo

Orcid: 0000-0003-3743-3689

According to our database1, Elisardo Antelo authored at least 45 papers between 1993 and 2019.

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Bibliography

2019
ENBB Processor: Towards the ExaScale Numerical Brain Box [Position Paper].
CoRR, 2019

New 3D Projection Transformation for Point Clouds.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2017
Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A Sum Error Detection Scheme for Decimal Arithmetic.
Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017

A Number System Approach for Adder Topologies.
Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017

2016
Asymmetric Allocation in a Shared Flexible Signature Module for Multicore Processors.
Comput. J., 2016

2014
Fast Radix-10 Multiplication Using Redundant BCD Codes.
IEEE Trans. Computers, 2014

2012
Redundant Floating-Point Decimal CORDIC Algorithm.
IEEE Trans. Computers, 2012

Guest Editors' Introduction: Special Section on Computer Arithmetic.
IEEE Trans. Computers, 2012

FlexSig: Implementing flexible hardware signatures.
ACM Trans. Archit. Code Optim., 2012

2011
Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers.
IEEE Trans. Computers, 2011

2010
Improved Design of High-Performance Parallel Decimal Multipliers.
IEEE Trans. Computers, 2010

2009
A Comment on "Beyond Fat-tree: Unidirectional Load-Balanced Multistage Interconnection Network".
IEEE Comput. Archit. Lett., 2009

Computation of Decimal Transcendental Functions Using the CORDIC Algorithm.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

A High-Performance Significand BCD Adder with IEEE 754-2008 Decimal Rounding.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

2008
A Low-Latency Pipelined 2D and 3D CORDIC Processors.
IEEE Trans. Computers, 2008

New insights on Ling adders.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007
A radix-10 SRT divider based on alternative BCD codings.
Proceedings of the 25th International Conference on Computer Design, 2007

A New Family of High.Performance Parallel Decimal Multipliers.
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 2007

2005
High-Throughput CORDIC-Based Geometry Operations for 3D Computer Graphics.
IEEE Trans. Computers, 2005

Digit-Recurrence Dividers with Reduced Logical Depth.
IEEE Trans. Computers, 2005

Low Latency Pipelined Circular CORDIC.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2003
Implementation of the Exponential Function in a Floating-Point Unit.
J. VLSI Signal Process., 2003

Radix-4 Reciprocal Square-Root and Its Combination with Division and Square Root.
IEEE Trans. Computers, 2003

2002
Fast Radix-4 Retimed Division with Selection by Comparisons.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001
Correctly Rounded Reciprocal Square-Root by Digit Recurrence and Radix-4 Implementation.
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

2000
CORDIC-Based Computation of ArcCos.
J. VLSI Signal Process., 2000

Very-High Radix CORDIC Rotation Based on Selection by Rounding.
J. VLSI Signal Process., 2000

Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring.
IEEE Trans. Computers, 2000

1999
Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding.
Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

1998
Radix-4 Vectoring CORDIC Algorithm and Architectures.
J. VLSI Signal Process., 1998

A novel design of a two operand normalization circuit.
IEEE Trans. Very Large Scale Integr. Syst., 1998

CORDIC Vectoring with Arbitrary Target Value.
IEEE Trans. Computers, 1998

Computation of sqrt(x/d) in a Very High Radix Combined Division/Square-Root Unit with Scaling.
IEEE Trans. Computers, 1998

1997
High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm.
IEEE Trans. Computers, 1997

Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm.
IEEE Trans. Computers, 1997

CORDIC-based computation of arccos and arcsin.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996
Unified Mixed Radix 2-4 Redundant CORDIC Processor.
IEEE Trans. Computers, 1996

High Radix Cordic Rotation Based on Selection by Rounding.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

Radix-4 Vectoring Cordic Algorithm And Architectures.
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

1995
CORDIC Architectures with Parallel Compensation of the Scale Factor.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

Digit On-line Large Radix CORDIC Rotator.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

Redundant CORDIC Rotator Based on Parallel Prediction.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1993
Design of a Pipelined Radix 4 CORDIC Processor.
Parallel Comput., 1993


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