Julio Villalba

According to our database1, Julio Villalba authored at least 56 papers between 1995 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Floating-Point Fused Multiply-Add under HUB Format.
Proceedings of the 27th IEEE Symposium on Computer Arithmetic, 2020

2019
Fast HUB Floating-Point Adder for FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Reproducible Summation Under HUB Format.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2018
Unbiased Rounding for HUB Floating-Point Addition.
IEEE Trans. Computers, 2018

2017
HUB Floating Point for Improving FPGA Implementations of DSP Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Introduction to the Special Issue on Computer Arithmetic.
IEEE Trans. Computers, 2017

Floating Point Square Root under HUB Format.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016
Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest.
IEEE Trans. Very Large Scale Integr. Syst., 2016

New Formats for Computing with Real-Numbers under Round-to-Nearest.
IEEE Trans. Computers, 2016

Decimal Multiformat Online Addition.
IEEE Trans. Computers, 2016

Digit Recurrence Floating-Point Division under HUB Format.
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

2015
Simplified floating-point units for high dynamic range image and video systems.
Proceedings of the International Symposium on Consumer Electronics, 2015

2014
Optimizing DSP circuits by a new family of arithmetic operators.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
Multioperand Redundant Adders on FPGAs.
IEEE Trans. Computers, 2013

Efficient floating-point representation for balanced codes for FPGA devices.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012
Radix-2 Multioperand and Multiformat Streaming Online Addition.
IEEE Trans. Computers, 2012

Redundant Floating-Point Decimal CORDIC Algorithm.
IEEE Trans. Computers, 2012

On-line Decimal Adder with RBCD Representation.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

Decimal online multioperand addition.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
High-Speed Algorithms and Architectures for Range Reduction Computation.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
Enhanced Scaling-Free CORDIC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

UCORE: Reconfigurable Platform for Educational Purposes.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

2009
Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Efficient Implementation of Carry-Save Adders in FPGAs.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

Computation of Decimal Transcendental Functions Using the CORDIC Algorithm.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

2008
Pipelined Architecture for Additive Range Reduction.
J. Signal Process. Syst., 2008

A Low-Latency Pipelined 2D and 3D CORDIC Processors.
IEEE Trans. Computers, 2008

New SIMD instructions set for image processing applications enhancement.
Proceedings of the International Conference on Image Processing, 2008

SIMD Enhancements for a Hough Transform Implementation.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Improving the Throughput of On-line Addition for Data Streams.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations.
IEEE Trans. Computers, 2006

SAD computation based on online arithmetic for motion estimation.
Microprocess. Microsystems, 2006

Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Pipelined Range Reduction for Floating Point Numbers.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
On-line Multioperand Addition Based on On-line Full Adders.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Low Latency Pipelined Circular CORDIC.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004
CORDIC Processor for Variable-Precision Interval Arithmetic.
J. VLSI Signal Process., 2004

Evaluation of Elementary Functions Using Multimedia Features.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Minimum Sum of Absolute Differences Implementation in a Single FPGA Device.
Proceedings of the Field Programmable Logic and Application, 2004

2002
Polynomial Evaluation on Multimedia Processors.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2000
MMX-Like Architecture Extension to Support the Rotation Operation.
Proceedings of the 2000 IEEE International Conference on Multimedia and Expo, 2000

A Hardware Algorithm for Variable-Precision Logarithm.
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999
Arithmetic Unit for the Computation of Interval Elementary Functions.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm.
Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

1998
Radix-4 Vectoring CORDIC Algorithm and Architectures.
J. VLSI Signal Process., 1998

Parallel Compensation of Scale Factor for the CORDIC Algorithm.
J. VLSI Signal Process., 1998

A Hardware Approach to Interval Arithmetic for Sine and Cosine Functions.
Proceedings of the Developments in Reliable Computing, 1998

1997
High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm.
IEEE Trans. Computers, 1997

Low latency word serial CORDIC.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996
Cordic based parallel/pipelined architecture for the Hough transform.
J. VLSI Signal Process., 1996

High Radix Cordic Rotation Based on Selection by Rounding.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

Radix-4 Vectoring Cordic Algorithm And Architectures.
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

1995
A fast Hough transform for segment detection.
IEEE Trans. Image Process., 1995

CORDIC Architectures with Parallel Compensation of the Scale Factor.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

Digit On-line Large Radix CORDIC Rotator.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

Redundant CORDIC Rotator Based on Parallel Prediction.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995


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