Lois Orosa
Orcid: 0000-0001-6773-6395Affiliations:
- ETH Zürich, Switzerland
According to our database1,
Lois Orosa
authored at least 41 papers
between 2012 and 2023.
Collaborative distances:
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Bibliography
2023
DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
IEEE Trans. Emerg. Top. Comput., 2023
2022
Dataset, July, 2022
J. Parallel Distributed Comput., 2022
NEON: Enabling Efficient Support for Nonlinear Operations in Resistive RAM-based Neural Network Accelerators.
CoRR, 2022
EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Accelerators.
CoRR, 2022
HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices.
Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022
2021
A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses.
CoRR, 2021
pLUTo: In-DRAM Lookup Tables to Enable Massively Parallel General-Purpose Computation.
CoRR, 2021
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks.
IEEE Access, 2021
A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chipsand Implications on Future Attacks and Defenses.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021
2020
Robust Machine Learning Systems: Challenges, Current Trends, Perspectives, and the Road Ahead.
IEEE Des. Test, 2020
Proceedings of the 32nd IEEE International Symposium on Computer Architecture and High Performance Computing, 2020
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Evanesco: Architectural Support for Efficient Data Sanitization in Modern Flash-Based Storage Systems.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020
2019
ACM Trans. Archit. Code Optim., 2019
AVPP: Address-first Value-next Predictor with Value Prefetching for Improving the Efficiency of Load Value Prediction.
ACM Trans. Archit. Code Optim., 2019
EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
2018
D-RaNGe: Violating DRAM Timing Constraints for High-Throughput True Random Number Generation using Commodity DRAM Devices.
CoRR, 2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
2016
Asymmetric Allocation in a Shared Flexible Signature Module for Multicore Processors.
Comput. J., 2016
Proceedings of the 24th Euromicro International Conference on Parallel, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016
2012
ACM Trans. Archit. Code Optim., 2012