Régis Leveugle
According to our database1,
Régis Leveugle
authored at least 136 papers
between 1989 and 2022.
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Bibliography
2022
Using Application Profiling based on a Virtual Platform for SoC Fault Tolerance Assessment.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
Recovering Information on the CVA6 RISC-V CPU with a Baremetal Micro-Architectural Covert Channel.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
2021
Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021
Proceedings of the IEEE International Test Conference, 2021
2020
A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the IEEE European Test Symposium, 2020
Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020
2019
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
2018
Hardware Support for Security in the Internet of Things: From Lightweight Countermeasures to Accelerated Homomorphic Encryption.
Inf., 2018
The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model.
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018
2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017
2016
Dummy operations in scalar multiplication over elliptic curves: A tradeoff between security and performance.
Microprocess. Microsystems, 2016
Analysis of laser-induced errors: RTL fault models versus layout locality characteristics.
Microprocess. Microsystems, 2016
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016
Evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 11th International Design & Test Symposium, 2016
Proceedings of the 11th International Design & Test Symposium, 2016
Tutorial 1: "New approaches towards early dependability evaluation of digital integrated systems".
Proceedings of the 11th International Design & Test Symposium, 2016
HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015
2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014
IDSM: An improved disjoint signature monitoring scheme for processor behavioral checking.
Proceedings of the 15th Latin American Test Workshop, 2014
Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014
Electromagnetic attacks on embedded devices: A model of probe-circuit power coupling.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Forecasting the Effects of Electromagnetic Fault Injections on Embedded Cryptosystems.
Inf. Secur. J. A Glob. Perspect., 2013
J. Electron. Test., 2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
2012
Proceedings of the 13th Latin American Test Workshop, 2012
2011
Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA.
J. Cryptol., 2011
Proceedings of the Interactive Theorem Proving - Second International Conference, 2011
10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Impact of Software Optimization on Variable Lifetimes in a Microprocessor-Based System.
Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011
2010
A new methodology for accurate predictive robustness analysis of designs implemented in SRAM-based FPGAs.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Early Robustness Evaluation of Digital Integrated Systems.
Proceedings of the 2010 Forum on specification & Design Languages, 2010
Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA.
Proceedings of the 15th European Test Symposium, 2010
Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010
2009
Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Trans. Computers, 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE Trans. Computers, 2007
Configuration errors analysis in SRAM-based FPGAs: Software tool and practical results.
Microelectron. Reliab., 2007
Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the Fourth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Experimental evaluation of protections against laser-induced faults and consequences on fault modeling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic.
IEEE Trans. Computers, 2006
Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the Fault Diagnosis and Tolerance in Cryptography, 2006
Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
2005
Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation.
J. Electron. Test., 2005
On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the Embedded and Ubiquitous Computing, 2005
Proceedings of the 42nd Design Automation Conference, 2005
2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow.
Proceedings of the 2004 Design, 2004
2003
IEEE Trans. Instrum. Meas., 2003
Microelectron. J., 2003
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments.
J. Electron. Test., 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
2002
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance.
Proceedings of the 2002 Design, 2002
2001
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
1999
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999
1997
Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
1995
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
1994
The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis.
IEEE Trans. Computers, 1994
Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
Alternative Approaches to Fault Detection in FSMs.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994
1993
Test of single fault tolerant controllers in VLSI circuits.
Proceedings of the VLSI 93, 1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Proceedings of the Digest of Papers: FTCS-23, 1993
Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
1992
Clocking scheme selection for circuits made up of a controller and a datapath.
Proceedings of the Synthesis for Control Dominated Circuits, 1992
Generation of optimized datapaths: bit-slice versus standard cells.
Proceedings of the Synthesis for Control Dominated Circuits, 1992
Synthesis of large controllers using ROM or PLA generators.
Proceedings of the Synthesis for Control Dominated Circuits, 1992
Logic Synthesis for Automatic Layout.
Proceedings of the Synthesis for Control Dominated Circuits, 1992
1991
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991
Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991
1990
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990
1989
Proceedings of the Proceedings International Test Conference 1989, 1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989