Régis Leveugle

According to our database1, Régis Leveugle authored at least 120 papers between 1989 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

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Links

On csauthors.net:

Bibliography

2018
Hardware Support for Security in the Internet of Things: From Lightweight Countermeasures to Accelerated Homomorphic Encryption.
Information, 2018

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

2017
Reliability of computing systems: From flip flops to variables.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

HLS design of a hardware accelerator for Homomorphic Encryption.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016
Dummy operations in scalar multiplication over elliptic curves: A tradeoff between security and performance.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

Analysis of laser-induced errors: RTL fault models versus layout locality characteristics.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

On fault injections for early security evaluation vs. laser-based attacks.
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016

Evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Taking into account indirect jumps or calls in continuous control-flow checking.
Proceedings of the 11th International Design & Test Symposium, 2016

A flexible RNS-based large polynomial multiplier for Fully Homomorphic Encryption.
Proceedings of the 11th International Design & Test Symposium, 2016

Tutorial 1: "New approaches towards early dependability evaluation of digital integrated systems".
Proceedings of the 11th International Design & Test Symposium, 2016

HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

On the development of a new countermeasure based on a laser attack RTL fault model.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Polynomial multipliers for fully homomorphic encryption on FPGA.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Validation of RTL laser fault injection model with respect to layout information.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

2014
Electromagnetic analysis and fault injection onto secure circuits.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014


Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014


IDSM: An improved disjoint signature monitoring scheme for processor behavioral checking.
Proceedings of the 15th Latin American Test Workshop, 2014

Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

On error models for RTL security evaluations.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Electromagnetic attacks on embedded devices: A model of probe-circuit power coupling.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

An Elliptic Curve Crypto-Processor Secured by Randomized Windows.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Forecasting the Effects of Electromagnetic Fault Injections on Embedded Cryptosystems.
Information Security Journal: A Global Perspective, 2013

Detailed Analysis of Compilation Options for Robust Software-based Embedded Systems.
J. Electronic Testing, 2013

Countermeasures against EM analysis for a secured FPGA-based AES implementation.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Automated design flow for no-cost configuration error detection in sram-based FPGAs.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Evaluating a low cost robustness improvement in SRAM-based FPGAs.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

An evaluation of an AES implementation protected against EM analysis.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012
Detailed analysis of compilation options for robust software-based embedded systems.
Proceedings of the 13th Latin American Test Workshop, 2012

Pattern-based injections in processors implemented on SRAM-based FPGAs.
Proceedings of the 13th Latin American Test Workshop, 2012

2011
Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA.
J. Cryptology, 2011

Towards Robustness Analysis Using PVS.
Proceedings of the Interactive Theorem Proving - Second International Conference, 2011

10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Impact of Software Optimization on Variable Lifetimes in a Microprocessor-Based System.
Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011

2010
A new methodology for accurate predictive robustness analysis of designs implemented in SRAM-based FPGAs.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Early Robustness Evaluation of Digital Integrated Systems.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA.
Proceedings of the 15th European Test Symposium, 2010

Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Towards automated fault pruning with Petri Nets.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Complementary Formal Approaches for Dependability Analysis.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Statistical fault injection: Quantified error and confidence.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Double-Data-Rate Computation as a Countermeasure against Fault Analysis.
IEEE Trans. Computers, 2008

Software Self-Testing of a Symmetric Cipher with Error Detection Capability.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Software BIST capabilities of a symmetric cipher.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Chip level security: Why ? How ?
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
CNTFET Modeling and Reconfigurable Logic-Circuit Design.
IEEE Trans. on Circuits and Systems, 2007

Early Analysis of Fault-based Attack Effects in Secure Circuits.
IEEE Trans. Computers, 2007

Configuration errors analysis in SRAM-based FPGAs: Software tool and practical results.
Microelectronics Reliability, 2007

Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

On Deratings to Refine System-Level Failure Rate Estimations.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Dependability issues in SRAM-based FPGA design.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection.
Proceedings of the Fourth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2007

Effective Checkpoint and Rollback Using Hardware/OS Collaboration.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Experimental evaluation of protections against laser-induced faults and consequences on fault modeling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic.
IEEE Trans. Computers, 2006

Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Error Detection Code Efficiency for Secure Chips.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Case Study of a Fault Attack on Asynchronous DES Crypto-Processors.
Proceedings of the Fault Diagnosis and Tolerance in Cryptography, 2006

Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

A Flexible SoPC-based Fault Injection Environment.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

On the Use of Information Redundancy When Designing Secure Chips.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation.
J. Electronic Testing, 2005

On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Hardening Techniques against Transient Faults for Asynchronous Circuits.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

On-Line Testing for Secure Implementations: Design and Validation.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Introduction to the Special Session on Secure Implementations.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Evaluation of SET and SEU Effects at Multiple Abstraction Levels.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Towards a Secure and Reliable System.
Proceedings of the Embedded and Ubiquitous Computing, 2005

Asynchronous circuits transient faults sensitivity evaluation.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Operating System Function Reuse to Achieve Low-Cost Fault Tolerance.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Asynchronous Circuits Sensitivity to Fault Injection.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

System-Level Dependability Analysis with RT-Level Fault Injection Accuracy.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow.
Proceedings of the 2004 Design, 2004

2003
Using run-time reconfiguration for fault injection applications.
IEEE Trans. Instrumentation and Measurement, 2003

Special section on defect and fault tolerance in VLSI systems.
Microelectronics Journal, 2003

Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments.
J. Electronic Testing, 2003

Dependability Analysis: A New Application for Run-Time Reconfiguration.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance.
Proceedings of the 2002 Design, 2002

2001
Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

High Level Modifications of VHDL Descriptions for On-Line Test or Fault Tolerance.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

A Low-Cost Hardware Approach to Dependability Validation of Ips.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
Fault Injection in VHDL Descriptions and Emulation.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999
Experiments on Multimedia Support of VLSI Design teaching in the MODEM Project.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999

1997
Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996
Standard and ROM-based synthesis of FSMs with control flow checking capabilities.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

ROM-Based Synthesis of Fault-Tolerant Controllers.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995
Design of defect-tolerant scan chains for MCMs with an active substrate.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

Efficient synthesis of fault-tolerant controllers.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis.
IEEE Trans. Computers, 1994

Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Taking Advantage of ASICs to Improve Dependability with Very Low Overheads.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Alternative Approaches to Fault Detection in FSMs.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993
Test of single fault tolerant controllers in VLSI circuits.
Proceedings of the VLSI 93, 1993

Influence of Error Correlations on the Signature Analysis Aliasing.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

A Synthesis Tool for Fault-Tolerant Finite State Machines.
Proceedings of the Digest of Papers: FTCS-23, 1993

Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

Optimized State Assignment of single fault Tolerant FSMs Based on SEC Codes.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Clocking scheme selection for circuits made up of a controller and a datapath.
Proceedings of the Synthesis for Control Dominated Circuits, 1992

Generation of optimized datapaths: bit-slice versus standard cells.
Proceedings of the Synthesis for Control Dominated Circuits, 1992

Synthesis of large controllers using ROM or PLA generators.
Proceedings of the Synthesis for Control Dominated Circuits, 1992

Logic Synthesis for Automatic Layout.
Proceedings of the Synthesis for Control Dominated Circuits, 1992

1991
Hierarchical Test Generation Based on Delayed Propagation.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

A New Approach to Control Flow Checking Without Program Modification.
Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

1990
Optimized Synthesis of Concurrently Checked Controllers.
IEEE Trans. Computers, 1990

Design of microprocessors with built-in on-line test.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

1989
Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities.
Proceedings of the Proceedings International Test Conference 1989, 1989


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