Görschwin Fey

According to our database1, Görschwin Fey authored at least 143 papers between 2003 and 2019.

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Bibliography

2019
Self-Explaining Digital Systems - Some Technical Steps.
Proceedings of the 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019

Approximation of Neural Networks for Verification.
Proceedings of the 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019

Symbolic Circuit Analysis under an Arc Based Timing Model.
Proceedings of the 24th IEEE European Test Symposium, 2019

2018
Design Understanding: From Logic to Specification*.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

Mining Latency Guarantees for RTL Designs.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

Augmenting All Solution SAT Solving for Circuits with Structural Information.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

Software-Level TMR Approach for On-Board Data Processing in Space Applications.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017
metaSMT: focus on your application and not on solver integration.
STTT, 2017

A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms.
J. Electronic Testing, 2017

Counterexample-Guided EF Synthesis of Boolean Functions.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Temporal redundancy latch-based architecture for soft error mitigation.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Mapping abstract and concrete hardware models for design understanding.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Property mining using dynamic dependency graphs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Debugging hardware designs using dynamic dependency graphs.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

WCET overapproximation for software in the context of a Cyber-Physical System.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Umgebung für automatisierte Tests von Dateisystemen auf NAND-Flash-Speichern.
Proceedings of the Internet der Dinge, 2016

Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables.
Proceedings of the 17th Latin-American Test Symposium, 2016

Counterexample-guided diagnosis.
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016

A Hybrid Algorithm to Conservatively Check the Robustness of Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

On the robustness of DCT-based compression algorithms for space applications.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Exact diagnosis using boolean satisfiability.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Multilevel design understanding: from specification to logic (invited paper).
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Equivalence checking on ESL utilizing a priori knowledge.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

Designing reliable cyber-physical systems overview associated to the special session at FDL'16.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

A hybrid algorithm to conservatively check the robustness of circuits.
Proceedings of the 21th IEEE European Test Symposium, 2016

Exploiting error detection latency for parity-based soft error detection.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

SMT-Based CPS Parameter Synthesis.
Proceedings of the ARCH@CPSWeek 2016, 2016

2015
Path-Based Program Repair.
Proceedings of the Proceedings 12th International Workshop on Formal Engineering approaches to Software Components and Architectures, 2015

Formal Verification of Robustness.
Proceedings of the Formal Modeling and Verification of Cyber-Physical Systems, 2015

In-circuit Error Detection with Software-based Error Correction - An Alternative to TMR.
Proceedings of the Formal Modeling and Verification of Cyber-Physical Systems, 2015

Empirical results on parity-based soft error detection with software-based retry.
Proceedings of the Nordic Circuits and Systems Conference, 2015

Execution Tracing of C Code for Formal Analysis (Extended Abstract).
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2015

Conservatively Analyzing Transient Faults.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Parity-based Soft Error Detection with Software-based Retry vs. Triplication-based Soft Error Correction - An Analytical Comparison on a Flash-based FPGA Architecture.
Proceedings of the 45. Jahrestagung der Gesellschaft für Informatik, Informatik 2015, Informatik, Energie und Umwelt, 28. September, 2015

Equivalence Checking on System Level Using a Priori Knowledge.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
A Simulation-Based Approach for Automated Feature Localization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Debug Automation for Synchronization Bugs at RTL.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Mutation Based Feature Localization.
Proceedings of the 15th International Microprocessor Test and Verification Workshop, 2014

Equivalence Checking on System Level using Stepwise Induction.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

A Logic for Cardinality Constraints (Extended Abstract).
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

SAT-based speedpath debugging using X traces.
Proceedings of the 9th International Design and Test Symposium, 2014

MetaSMT: a unified interface to SMT-LIB2.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

Sat-based speedpath debugging using waveforms.
Proceedings of the 19th IEEE European Test Symposium, 2014

Automatically connecting hardware blocks via light-weight matching techniques.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013
Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis.
ECEASST, 2013

Debug Automation for Logic Circuits Under Timing Variations.
IEEE Design & Test, 2013

Yet a Better Error Explanation Algorithm (Extended Abstract).
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Debugging HDL designs based on functional equivalences with high-level specifications.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Efficient automated speedpath debugging.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Improving fault tolerance utilizing hardware-software-co-synthesis.
Proceedings of the Design, Automation and Test in Europe, 2013

Tuning dynamic data flow analysis to support design understanding.
Proceedings of the Design, Automation and Test in Europe, 2013

Reliability analysis reloaded: how will we survive?
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Verifying Reliability (Dagstuhl Seminar 12341).
Dagstuhl Reports, 2012

FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation.
Proceedings of the Model Checking Software - 19th International Workshop, 2012

Model-based diagnosis versus error explanation.
Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

Automated Feature Localization for Hardware Designs using Coverage Metrics.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012

FoREnSiC- An Automatic Debugging Environment for C Programs.
Proceedings of the Hardware and Software: Verification and Testing, 2012

Complete and effective robustness checking by means of interpolation.
Proceedings of the Formal Methods in Computer-Aided Design, 2012

Functional analysis of circuits under timing variations.
Proceedings of the 17th IEEE European Test Symposium, 2012

On Modeling and Evaluation of Logic Circuits under Timing Variations.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Automated debugging from pre-silicon to post-silicon.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Automated feature localization for hardware designs using coverage metrics.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Automated Post-Silicon Debugging of Failing Speedpaths.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Effective Robustness Analysis Using Bounded Model Checking Techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Assessing System Vulnerability Using Formal Verification Techniques.
Proceedings of the Mathematical and Engineering Methods in Computer Science, 2011

Towards Automatic Property Generation for the Formal Verification of Bus Bridges.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

Test Case Generation from Mutants Using Model Checking Techniques.
Proceedings of the Fourth IEEE International Conference on Software Testing, 2011

metaSMT: Focus on Your Application not on Solver Integration.
Proceedings of the First International Workshop on Design and Implementation of Formal Tools and Systems, 2011

Latency Analysis for Sequential Circuits.
Proceedings of the 16th European Test Symposium, 2011

Automated Design Debugging in a Testbench-Based Verification Environment.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Automatic property generation for the formal verification of bus bridges.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Orchestrated multi-level information flow analysis to understand SoCs.
Proceedings of the 48th Design Automation Conference, 2011

2010
Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits).
it - Information Technology, 2010

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics.
J. Electronic Testing, 2010

Towards Unifying Localization and Explanation for Automated Debugging.
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010

Using QBF to increase accuracy of SAT-based debugging.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Polynomial datapath optimization using constraint solving and formal modelling.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Evaluating Debugging Algorithms from a Qualitative Perspective.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

RobuCheck: A Robustness Checker for Digital Circuits.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

A better-than-worst-case robustness measure.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Formal verification meets robustness checking - Techniques and challenges.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation).
it - Information Technology, 2009

Advanced verification by automatic property generation.
IET Computers & Digital Techniques, 2009

WoLFram- A Word Level Framework for Formal Verification.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Increasing the Accuracy of SAT-based Debugging.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009

Evaluation of Cardinality Constraints on SMT-Based Debugging.
Proceedings of the ISMVL 2009, 2009

Robustness Check for Multiple Faults Using Formal Techniques.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Increasing the accuracy of SAT-based debugging.
Proceedings of the Design, Automation and Test in Europe, 2009

Computing bounds for fault tolerance using formal techniques.
Proceedings of the 46th Design Automation Conference, 2009

Deterministic Algorithms for ATPG under Leakage Constraints.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Test Pattern Generation using Boolean Proof Engines.
Springer, ISBN: 978-90-481-2359-9, 2009

2008
Automatic Fault Localization for Property Checking.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

On Acceleration of SAT-Based ATPG for Industrial Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Debugging Design Errors by Using Unsatisfiable Cores.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008

A Basis for Formal Robustness Checking.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Using unsatisfiable cores to debug multiple design errors.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Automatic Generation of Complex Properties for Hardware Designs.
Proceedings of the Design, Automation and Test in Europe, 2008

SAT-based Automatic Test Pattern Generation.
Proceedings of the Evolutionary Test Generation, 24.08. - 29.08.2008, 2008

Targeting Leakage Constraints during ATPG.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

Robustness and usability in modern design flows.
Springer, ISBN: 978-1-4020-6535-4, 2008

2007
Reusing Learned Information in SAT-based ATPG.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

SWORD: A SAT like Prover Using Word Level Information.
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

SWORD: A SAT like prover using word level information.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Formal Verification on the Word Level using SAT-like Proof Techniques.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Experimental Studies on SAT-Based ATPG for Gate Delay Faults.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

SAT-based ATPG for Path Delay Faults in Sequential Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

On the Construction of Small Fully Testable Circuits with Low Depth.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Instance Generation for SAT-based ATPG.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
Minimizing the number of paths in BDDs: Theory and algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

An Integrated Approach for Combining BDD and SAT Provers.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Automatic Test Pattern Generation.
Proceedings of the Formal Methods for Hardware Verification, 2006

SAT-based Calculation of Source Code Coverage for BMC.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

Efficiency of Multi-Valued Encoding in SAT-based ATPG.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

Automatic Fault Localization for Property Checking.
Proceedings of the Hardware and Software, 2006

Increasing robustness and usability of circuit design tools by using formal techniques.
Proceedings of the Ausgezeichnete Informatikdissertationen 2006, 2006

On the relation between simulation-based and SAT-based diagnosis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Avoiding false negatives in formal verification for protocol-driven blocks.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
SyCE: An Integrated Environment for System Design in SystemC.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Controlling the Memory During Manipulation of Word-Level Decision Diagrams.
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005

Utilizing don't care states in SAT-based bounded sequential problems.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Bridging fault testability of BDD circuits.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Advanced BDD optimization.
Springer, ISBN: 978-0-387-25453-1, 2005

2004
Synthesis of fully testable circuits from BDDs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Algorithms for Taylor Expansion Diagrams.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

Disjoint Sum of Product Minimization by Evolutionary Algorithms.
Proceedings of the Applications of Evolutionary Computing, 2004

BDD Circuit Optimization for Path Delay Fault Testability.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor.
Proceedings of the 2004 Design, 2004

Improving simulation-based verification by means of formal methods.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Finding Good Counter-Examples to Aid Design Verification.
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

Cost-efficient Formal Block Verification for ASIC Design.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

Modeling Multi-Valued Circuits in SystemC.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

MuTaTe: an efficient design for testability technique for multiplexor based circuits.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003


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