Xavier Vera

Proceedings of the IEEE Hot Chips 32 Symposium, 2020

2016

A Case for Acoustic Wave Detectors for Soft-Errors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

2014

Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Framework for economical error recovery in embedded cores.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

2013

Deconfigurable microprocessor architectures for silicon debug acceleration.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Reducing DUE-FIT of caches by exploiting acoustic wave detectors for error recovery.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Capturing vulnerability variations for register files.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Setting an error detection infrastructure with low cost acoustic wave detectors.

[BibT_eX]

[DOI]

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

2011

Implementing End-to-End Register Data-Flow Continuous Self-Test.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies.

[BibT_eX]

[DOI]

Proceedings of the 2nd European Future Technologies Conference and Exhibition, 2011

Design of complex circuits using the Via-Configurable transistor array regular layout fabric.

[BibT_eX]

[DOI]

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Accelerating microprocessor silicon validation by exposing ISA diversity.

[BibT_eX]

[DOI]

Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

New reliability mechanisms in memory design for sub-22nm technologies.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Hardware/software-based diagnosis of load-store queues using expandable activity logs.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Control-Flow Recovery Validation Using Microarchitectural Invariants.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Architectures for online error detection and recovery in multicore processors.

[BibT_eX]

[DOI]

Siva Kumar Sastry Hari

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Microarchitectural Online Testing for Failure Detection in Memory Order Buffers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Electromigration for microarchitects.

[BibT_eX]

[DOI]

ACM Comput. Surv., 2010

VCTA: A Via-Configurable Transistor Array regular fabric.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

MT-SBST: Self-test optimization in multithreaded multicore architectures.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

High-Performance low-vcc in-order core.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

The split register file.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Selective replication: A lightweight technique for soft errors.

[BibT_eX]

[DOI]

ACM Trans. Comput. Syst., 2009

Reducing Soft Errors through Operand Width Aware Policies.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2009

Low Vccmin fault-tolerant cache with highly predictable performance.

[BibT_eX]

[DOI]

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

End-to-end register data-flow continuous self-test.

[BibT_eX]

[DOI]

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Online error detection and correction of erratic bits in register files.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

DFx for massively multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008

Refueling: Preventing Wire Degradation due to Electromigration.

[BibT_eX]

[DOI]

IEEE Micro, 2008

On-line Failure Detection in Memory Order Buffers.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

On-Line Failure Detection and Confinement in Caches.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Issue system protection mechanisms.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

2007

Data cache locking for tight timing calculations.

[BibT_eX]

[DOI]

Björn Lisper

ACM Trans. Embed. Comput. Syst., 2007

Penelope: The NBTI-Aware Processor.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Surviving to Errors in Multi-Core Environments.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Fuse: A Technique to Anticipate Failures due to Degradation in ALUs.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

2006

Impact of Parameter Variations on Circuits and Microarchitecture.

[BibT_eX]

[DOI]

IEEE Micro, 2006

Exploiting Narrow Values for Soft Error Tolerance.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2006

Empowering a helper cluster through data-width aware instruction selection policies.

[BibT_eX]

[DOI]

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2005

An accurate cost model for guiding data locality transformations.

[BibT_eX]

[DOI]

ACM Trans. Program. Lang. Syst., 2005

IATAC: a smart predictor to turn-off L2 cache lines.

[BibT_eX]

[DOI]

Michael F. P. O'Boyle

ACM Trans. Archit. Code Optim., 2005

Variable-Based Multi-module Data Caches for Clustered VLIW Processors.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

2004

A fast and accurate framework to analyze and optimize cache memory behavior.

[BibT_eX]

[DOI]

ACM Trans. Program. Lang. Syst., 2004

Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2004

2003

Data cache locking for higher program predictability.

[BibT_eX]

[DOI]

Björn Lisper

Proceedings of the International Conference on Measurements and Modeling of Computer Systems, 2003

Data Caches in Multitasking Hard Real-Time Systems.

[BibT_eX]

[DOI]

Björn Lisper

Proceedings of the 24th IEEE Real-Time Systems Symposium (RTSS 2003), 2003

Code Tiling for Improving the Cache Performance of PDE Solvers.

[BibT_eX]

[DOI]

Qingguang Huang

Proceedings of the 32nd International Conference on Parallel Processing (ICPP 2003), 2003

Optimizing Program Locality Through CMEs and GAs.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003

2002

Near-Optimal Padding for Removing Conflict Misses.

[BibT_eX]

[DOI]

Josep Llosa

Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002

Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on Parallel Processing Workshops (ICPP 2002 Workshops), 2002

Let's Study Whole-Program Cache Behaviour Analytically.

[BibT_eX]

[DOI]