Enrique Vallejo

IEEE Des. Test, 2022

2021

S-SMART++: A Low-Latency NoC Leveraging Speculative Bypass Requests.

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[DOI]

IEEE Trans. Computers, 2021

PIugSMART: a pluggable open-source module to implement multihop bypass in networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021

2020

Efficient bypass in mesh and torus NoCs.

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[DOI]

J. Syst. Archit., 2020

BST: A BookSim-Based Toolset to Simulate NoCs with Single- and Multi-Hop Bypass.

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[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

2019

ACOR: Adaptive congestion-oblivious routing in dragonfly networks.

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[DOI]

J. Parallel Distributed Comput., 2019

Non-minimal adaptive routing based on explicit congestion notifications.

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[DOI]

Concurr. Comput. Pract. Exp., 2019

SMART++: reducing cost and improving efficiency of multi-hop bypass in NoC routers.

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[DOI]

Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

Lagarto I RISC-V Multi-core: Research Challenges to Build and Integrate a Network-on-Chip.

[BibT_eX]

[DOI]

Neiel I. Leyva-Santes

César-Alejandro Hernández-Calderón

Miquel Moretó

Marco Antonio Ramírez Salinas

Luis A. Villa-Vargas

Proceedings of the Supercomputing, 2019

Impact of Network Fairness on the Performance of Parallel Systems.

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[DOI]

Cruz Izu

Proceedings of the Australasian Computer Science Week Multiconference, 2019

2018

Efficient Router Bypass via Hybrid Flow Control.

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[DOI]

Proceedings of the 11th International Workshop on Network on Chip Architectures, 2018

Architectural Support for Task Dependence Management with Flexible Software Scheduling.

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[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

Analysis and Improvement of Valiant Routing in Low-Diameter Networks.

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[DOI]

Proceedings of the 4th IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era, 2018

2017

Projective Networks: Topologies for Large Parallel Computer Systems.

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[DOI]

IEEE Trans. Parallel Distributed Syst., 2017

A scalable synthetic traffic model of Graph500 for computer networks analysis.

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[DOI]

Concurr. Comput. Pract. Exp., 2017

FlexVC: Flexible Virtual Channel Management in Low-Diameter Networks.

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[DOI]

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Extending Commodity OpenFlow Switches for Large-Scale HPC Deployments.

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[DOI]

Proceedings of the 3rd IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era, 2017

2016

Network unfairness in dragonfly topologies.

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[DOI]

J. Supercomput., 2016

The mont-blanc prototype: an alternative approach for HPC systems.

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[DOI]

Proceedings of the International Conference for High Performance Computing, 2016

CATA: Criticality Aware Task Acceleration for Multicore Processors.

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[DOI]

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

Synthetic Traffic Model of the Graph500 Communications.

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[DOI]

Proceedings of the Algorithms and Architectures for Parallel Processing, 2016

2015

On-the-fly adaptive routing for dragonfly interconnection networks.

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[DOI]

J. Supercomput., 2015

Contention-Based Nonminimal Adaptive Routing in High-Radix Networks.

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[DOI]

Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium, 2015

Performance optimization of load imbalanced workloads in large scale Dragonfly systems.

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[DOI]

Proceedings of the 16th IEEE International Conference on High Performance Switching and Routing, 2015

On the Use of Commodity Ethernet Technology in Exascale HPC Systems.

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[DOI]

Mariano Benito

Proceedings of the 22nd IEEE International Conference on High Performance Computing, 2015

Throughput Unfairness in Dragonfly Networks under Realistic Traffic Patterns.

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[DOI]

Proceedings of the 2015 IEEE International Conference on Cluster Computing, 2015

2014

Topological Characterization of Hamming and Dragonfly Networks and Its Implications on Routing.

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[DOI]

Cristobal Camarero

ACM Trans. Archit. Code Optim., 2014

Performance implications of remote-only load balancing under adversarial traffic in Dragonflies.

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[DOI]

Proceedings of the 8th International Workshop on Interconnection Network Architecture, 2014

2013

Task mapping in rectangular twisted tori.

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[DOI]

Proceedings of the 2013 Spring Simulation Multiconference, SpringSim '13, 2013

Efficient Routing Mechanisms for Dragonfly Networks.

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[DOI]

Proceedings of the 42nd International Conference on Parallel Processing, 2013

OFAR-CM: Efficient Dragonfly Networks with Simple Congestion Management.

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[DOI]

Proceedings of the IEEE 21st Annual Symposium on High-Performance Interconnects, 2013

Global misrouting policies in two-level hierarchical networks.

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[DOI]

Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, 2013

2012

Throughput Fairness in Indirect Interconnection Networks.

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[DOI]

Cruz Izu

Proceedings of the 13th International Conference on Parallel and Distributed Computing, 2012

Comparison Study of Scalable and Cost-Effective Interconnection Networks for HPC.

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[DOI]

Proceedings of the 41st International Conference on Parallel Processing Workshops, 2012

On-the-Fly Adaptive Routing in High-Radix Hierarchical Networks.

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[DOI]

Proceedings of the 41st International Conference on Parallel Processing, 2012

2011

Hybrid Transactional Memory with Pessimistic Concurrency Control.

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[DOI]

Int. J. Parallel Program., 2011

2010

Twisted Torus Topologies for Enhanced Interconnection Networks.

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[DOI]

IEEE Trans. Parallel Distributed Syst., 2010

Architectural Support for Fair Reader-Writer Locking.

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[DOI]

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

2007

Mixed-radix Twisted Torus Interconnection Networks.

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[DOI]

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Implicit Transactional Memory in Kilo-Instruction Multiprocessors.

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[DOI]

Proceedings of the Advances in Computer Systems Architecture, 2007

2006

Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors.

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[DOI]

Int. J. Parallel Program., 2006

2005

Practicable Layouts for Optimal Circulant Graphs.

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[DOI]