Javier Navaridas

Orcid: 0000-0001-7272-6597

According to our database1, Javier Navaridas authored at least 79 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Understanding the Impact of Arbitration in MZI-Based Beneš Switching Fabrics.
IEEE Trans. Parallel Distributed Syst., February, 2024

2023
GöwFed: A novel federated network intrusion detection system.
J. Netw. Comput. Appl., 2023

Parallelizing Multipacting Simulation for the Design of Particle Accelerator Components.
Proceedings of the 31st Euromicro International Conference on Parallel, 2023

A Novel Simulation Methodology for Silicon Photonic Switching Fabrics.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

SiliconBurmuin: A Horizon Europe propelled Neurocomputing Initiative in the Basque Country.
Proceedings of the 49th Euromicro Conference on Software Engineering and Advanced Applications, 2023

2022
A review of Federated Learning in Intrusion Detection Systems for IoT.
CoRR, 2022

2021
On the routing and scalability of MZI-based optical Beneš interconnects.
Nano Commun. Networks, 2021

Power and energy efficient routing for Mach-Zehnder interferometer based photonic switches.
Proceedings of the ICS '21: 2021 International Conference on Supercomputing, 2021

2020
Analysis of software and hardware-accelerated approaches to the simulation of unconventional interconnection networks.
Simul. Model. Pract. Theory, 2020

Toward FPGA-Based HPC: Advancing Interconnect Technologies.
IEEE Micro, 2020

Relating the bisection width of dual-port, server-centric datacenter networks and the solution of edge isoperimetric problems in graphs.
J. Comput. Syst. Sci., 2020

Message from the Conference Chairs - ASAP 2020.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019
INRFlow: An interconnection networks research flow-level simulation framework.
J. Parallel Distributed Comput., 2019

Can the Optimizer Cost be Used to Predict Query Execution Times?
CoRR, 2019

On the effects of allocation strategies for exascale computing systems with distributed storage and unified interconnects.
Concurr. Comput. Pract. Exp., 2019

Enabling shared memory communication in networks of MPSoCs.
Concurr. Comput. Pract. Exp., 2019

Scalability analysis of optical Beneš networks based on thermally/electrically tuned Mach-Zehnder interferometers.
Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019

Robust Covert Channels Based on DRAM Power Consumption.
Proceedings of the Information Security - 22nd International Conference, 2019

Design Exploration of Multi-tier Interconnection Networks for Exascale Systems.
Proceedings of the 48th International Conference on Parallel Processing, 2019

Enabling Standalone FPGA Computing.
Proceedings of the 2019 IEEE Symposium on High-Performance Interconnects, 2019

Receive-Side Notification for Enhanced RDMA in FPGA Based Networks.
Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019

2018
Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development.
Microprocess. Microsystems, 2018

A Survey on Optical Network-on-Chip Architectures.
ACM Comput. Surv., 2018

High-Performance, Low-Complexity Deadlock Avoidance for Arbitrary Topologies/Routings.
Proceedings of the 32nd International Conference on Supercomputing, 2018

Network-on-chip evaluation for a novel neural architecture.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

A CAM-Free Exascalable HPC Router for Low-Energy Communications.
Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2017
Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2017

An Optimal Single-Path Routing Algorithm in the Datacenter Network DPillar.
IEEE Trans. Parallel Distributed Syst., 2017

Efficient Sharing of Optical Resources in Low-Power Optical Networks-on-Chip.
JOCN, 2017

Improved routing algorithms in the dual-port datacenter networks HCN and BCN.
Future Gener. Comput. Syst., 2017

The stellar transformation: From interconnection networks to datacenter networks.
Comput. Networks, 2017

Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Subchannel Scheduling for Shared Optical On-chip Buses.
Proceedings of the 25th IEEE Annual Symposium on High-Performance Interconnects, 2017

On the Effects of Data-Aware Allocation on Fully Distributed Storage Systems for Exascale.
Proceedings of the Euro-Par 2017: Parallel Processing Workshops, 2017


Designing an exascale interconnect using multi-objective optimization.
Proceedings of the 2017 IEEE Congress on Evolutionary Computation, 2017

2016
A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip.
ACM Comput. Surv., 2016

Cyclic Power-Gating as an Alternative to Voltage and Frequency Scaling.
IEEE Comput. Archit. Lett., 2016


2015
SpiNNaker: Enhanced multicast routing.
Parallel Comput., 2015

Star-Replaced Networks: A Generalised Class of Dual-Port Server-Centric Data Centre Networks.
CoRR, 2015

An efficient shortest-path routing algorithm in the data centre network {DP}illar.
CoRR, 2015

Routing Algorithms for Recursively-Defined Data Centre Networks.
Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015

Analysis of FPGA and software approaches to simulate unconventional computer architectures.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

CHO: towards a benchmark suite for OpenCL FPGA accelerators.
Proceedings of the 3rd International Workshop on OpenCL, 2015

On Routing Algorithms for the DPillar Data Centre Networks.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

Amon: An Advanced Mesh-like Optical NoC.
Proceedings of the 23rd IEEE Annual Symposium on High-Performance Interconnects, 2015

Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

An Efficient Shortest-Path Routing Algorithm in the Data Centre Network DPillar.
Proceedings of the Combinatorial Optimization and Applications, 2015

Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014
Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes.
Microprocess. Microsystems, 2014

An empirical evaluation of High-Level Synthesis languages and tools for database acceleration.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

On generating multicast routes for SpiNNaker.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2013
SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture.
Parallel Comput., 2013

Transient Fault Tolerant QDI Interconnects Using Redundant Check Code.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Scalable communications for a million-core neural processing architecture.
J. Parallel Distributed Comput., 2012

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System.
Int. J. Parallel Program., 2012

Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Population-based routing in the SpiNNaker neuromorphic architecture.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

2011
Simulating and evaluating interconnection networks with INSEE.
Simul. Model. Pract. Theory, 2011

Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric.
Parallel Comput., 2011

Indirect cube: A power-efficient topology for compute clusters.
Opt. Switch. Netw., 2011

2010
Twisted Torus Topologies for Enhanced Interconnection Networks.
IEEE Trans. Parallel Distributed Syst., 2010

Reducing complexity in tree-like computer interconnection networks.
Parallel Comput., 2010

SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
Interconnection Network Simulation Using Traces of MPI Applications.
Int. J. Parallel Program., 2009

Full-system simulation of distributed memory multicomputers.
Clust. Comput., 2009

Effects of Job and Task Placement on Parallel Scientific Applications Performance.
Proceedings of the 17th Euromicro International Conference on Parallel, 2009

Effects of Topology-Aware Allocation Policies on Scheduling Performance.
Proceedings of the Job Scheduling Strategies for Parallel Processing, 2009

Realistic Evaluation of Interconnection Networks Using Synthetic Traffic.
Proceedings of the Eighth International Symposium on Parallel and Distributed Computing, 2009

Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric.
Proceedings of the Eighth International Symposium on Parallel and Distributed Computing, 2009

Understanding the interconnection network of SpiNNaker.
Proceedings of the 23rd international conference on Supercomputing, 2009

2008
On synthesizing workloads emulating MPI applications.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

2007
Realistic Evaluation of Interconnection Network Performance at High Loads.
Proceedings of the Eighth International Conference on Parallel and Distributed Computing, 2007

Mixed-radix Twisted Torus Interconnection Networks.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Concepts and components of full-system simulation of distributed memory parallel computers.
Proceedings of the 16th International Symposium on High-Performance Distributed Computing (HPDC-16 2007), 2007

Evaluation of Interconnection Networks Using Full-System Simulators: Lessons Learned.
Proceedings of the Proceedings 40th Annual Simulation Symposium (ANSS-40 2007), 2007


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