Ramón Beivide

According to our database1, Ramón Beivide authored at least 126 papers between 1987 and 2023.

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Bibliography

2023
Parallelisation of decision-making techniques in aquaculture enterprises.
J. Supercomput., 2023

Analysing Mechanisms for Virtual Channel Management in Low-Diameter Networks.
Proceedings of the 35th IEEE International Symposium on Computer Architecture and High Performance Computing, 2023

2022
Polarized Routing for Large Interconnection Networks.
IEEE Micro, 2022

2021
S-SMART++: A Low-Latency NoC Leveraging Speculative Bypass Requests.
IEEE Trans. Computers, 2021

Sigmoid: An auto-tuned load balancing algorithm for heterogeneous systems.
J. Parallel Distributed Comput., 2021

PIugSMART: a pluggable open-source module to implement multihop bypass in networks-on-chip.
Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021

Polarized routing: an efficient and versatile algorithm for large direct networks.
Proceedings of the IEEE Symposium on High-Performance Interconnects, 2021

2020
Efficient bypass in mesh and torus NoCs.
J. Syst. Archit., 2020

EngineCL: Usability and Performance in Heterogeneous Computing.
Future Gener. Comput. Syst., 2020

BST: A BookSim-Based Toolset to Simulate NoCs with Single- and Multi-Hop Bypass.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

Modelling Standard and Randomized Slimmed Folded Clos Networks.
Proceedings of the Euro-Par 2020: Parallel Processing, 2020

2019
Load balancing in a heterogeneous world: CPU-Xeon Phi co-execution of data-parallel kernels.
J. Supercomput., 2019

Auto-tuned OpenCL kernel co-execution in OmpSs for heterogeneous systems.
J. Parallel Distributed Comput., 2019

ACOR: Adaptive congestion-oblivious routing in dragonfly networks.
J. Parallel Distributed Comput., 2019

Non-minimal adaptive routing based on explicit congestion notifications.
Concurr. Comput. Pract. Exp., 2019

Optimizing computation-communication overlap in asynchronous task-based programs: poster.
Proceedings of the 24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2019

SMART++: reducing cost and improving efficiency of multi-hop bypass in NoC routers.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

Lagarto I RISC-V Multi-core: Research Challenges to Build and Integrate a Network-on-Chip.
Proceedings of the Supercomputing, 2019

Towards Co-execution on Commodity Heterogeneous Systems: Optimizations for Time-Constrained Scenarios.
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019

Optimizing computation-communication overlap in asynchronous task-based programs.
Proceedings of the ACM International Conference on Supercomputing, 2019

2018
On Random Wiring in Practicable Folded Clos Networks for Modern Datacenters.
IEEE Trans. Parallel Distributed Syst., 2018

Efficient Router Bypass via Hybrid Flow Control.
Proceedings of the 11th International Workshop on Network on Chip Architectures, 2018

Architectural Support for Task Dependence Management with Flexible Software Scheduling.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

Analysis and Improvement of Valiant Routing in Low-Diameter Networks.
Proceedings of the 4th IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era, 2018

2017
Projective Networks: Topologies for Large Parallel Computer Systems.
IEEE Trans. Parallel Distributed Syst., 2017

Energy efficiency of load balancing for data-parallel applications in heterogeneous systems.
J. Supercomput., 2017

A scalable synthetic traffic model of Graph500 for computer networks analysis.
Concurr. Comput. Pract. Exp., 2017

Extending OmpSs for OpenCL Kernel Co-Execution in Heterogeneous Systems.
Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017

FlexVC: Flexible Virtual Channel Management in Low-Diameter Networks.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Random Folded Clos Topologies for Datacenter Networks.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Extending Commodity OpenFlow Switches for Large-Scale HPC Deployments.
Proceedings of the 3rd IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era, 2017

To Distribute or Not to Distribute: The Question of Load Balancing for Performance or Energy.
Proceedings of the Euro-Par 2017: Parallel Processing - 23rd International Conference on Parallel and Distributed Computing, Santiago de Compostela, Spain, August 28, 2017

2016
Assessing the Suitability of King Topologies for Interconnection Networks.
IEEE Trans. Parallel Distributed Syst., 2016

Network unfairness in dragonfly topologies.
J. Supercomput., 2016

Interconnection Networks in Petascale Computer Systems: A Survey.
ACM Comput. Surv., 2016


Simplifying programming and load balancing of data parallel applications on heterogeneous systems.
Proceedings of the 9th Annual Workshop on General Purpose Processing using Graphics Processing Unit, 2016

CATA: Criticality Aware Task Acceleration for Multicore Processors.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

Synthetic Traffic Model of the Graph500 Communications.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2016

2015
Lattice Graphs for High-Scale Interconnection Topologies.
IEEE Trans. Parallel Distributed Syst., 2015

On-the-fly adaptive routing for dragonfly interconnection networks.
J. Supercomput., 2015

Identifying codes of degree 4 Cayley graphs over Abelian groups.
Adv. Math. Commun., 2015

Contention-Based Nonminimal Adaptive Routing in High-Radix Networks.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium, 2015

Performance optimization of load imbalanced workloads in large scale Dragonfly systems.
Proceedings of the 16th IEEE International Conference on High Performance Switching and Routing, 2015

On the Use of Commodity Ethernet Technology in Exascale HPC Systems.
Proceedings of the 22nd IEEE International Conference on High Performance Computing, 2015

Throughput Unfairness in Dragonfly Networks under Realistic Traffic Patterns.
Proceedings of the 2015 IEEE International Conference on Cluster Computing, 2015

2014
Topological Characterization of Hamming and Dragonfly Networks and Its Implications on Routing.
ACM Trans. Archit. Code Optim., 2014

Source Misrouting in King Topologies.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

Performance implications of remote-only load balancing under adversarial traffic in Dragonflies.
Proceedings of the 8th International Workshop on Interconnection Network Architecture, 2014

Characterizing the Communication Demands of the Graph500 Benchmark on a Commodity Cluster.
Proceedings of the 1st IEEE/ACM International Symposium on Big Data Computing, 2014

2013
L-Networks: A Topological Model for Regular 2D Interconnection Networks.
IEEE Trans. Computers, 2013

On the trade-off of mixing scientific applications on capacity high-performance computing systems.
IET Comput. Digit. Tech., 2013

Symmetric Interconnection Networks from Cubic Crystal Lattices.
CoRR, 2013

Task mapping in rectangular twisted tori.
Proceedings of the 2013 Spring Simulation Multiconference, SpringSim '13, 2013

Efficient Routing Mechanisms for Dragonfly Networks.
Proceedings of the 42nd International Conference on Parallel Processing, 2013

OFAR-CM: Efficient Dragonfly Networks with Simple Congestion Management.
Proceedings of the IEEE 21st Annual Symposium on High-Performance Interconnects, 2013

Global misrouting policies in two-level hierarchical networks.
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, 2013

Advanced Switching Mechanisms for Forthcoming On-Chip Networks.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
The Network Adapter: The Missing Link between MPI Applications and Network Performance.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

Comparison Study of Scalable and Cost-Effective Interconnection Networks for HPC.
Proceedings of the 41st International Conference on Parallel Processing Workshops, 2012

On-the-Fly Adaptive Routing in High-Radix Hierarchical Networks.
Proceedings of the 41st International Conference on Parallel Processing, 2012

Performance implications of deadlock avoidance techniques in torus networks.
Proceedings of the 13th IEEE International Conference on High Performance Switching and Routing, 2012

King Topologies for Fault Tolerance.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Contention-aware node allocation policy for high-performance capacity systems.
Proceedings of the 2012 Interconnection Network Architecture, 2012

2011
Hybrid Transactional Memory with Pessimistic Concurrency Control.
Int. J. Parallel Program., 2011

2010
Twisted Torus Topologies for Enhanced Interconnection Networks.
IEEE Trans. Parallel Distributed Syst., 2010

Quotients of Gaussian graphs and their application to perfect codes.
J. Symb. Comput., 2010

Architectural Support for Fair Reader-Writer Locking.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Perfect graph codes over two dimensional lattices.
Proceedings of the IEEE International Symposium on Information Theory, 2010

A First Approach to King Topologies for On-Chip Networks.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

2009
Perfect codes from Cayley graphs over Lipschitz integers.
IEEE Trans. Inf. Theory, 2009

Exploring pattern-aware routing in generalized fat tree networks.
Proceedings of the 23rd international conference on Supercomputing, 2009

Light NUCA: A proposal for bridging the inter-cache latency gap.
Proceedings of the Design, Automation and Test in Europe, 2009

Oblivious routing schemes in extended generalized Fat Tree networks.
Proceedings of the 2009 IEEE International Conference on Cluster Computing, August 31, 2009

2008
Immunet: Dependable Routing for Interconnection Networks with Arbitrary Topology.
IEEE Trans. Computers, 2008

Modeling Toroidal Networks with the Gaussian Integers.
IEEE Trans. Computers, 2008

Modeling hexagonal constellations with Eisenstein-Jacobi graphs.
Probl. Inf. Transm., 2008

Graph-based metrics over QAM constellations.
Proceedings of the 2008 IEEE International Symposium on Information Theory, 2008

2007
Perfect Codes for Metrics Induced by Circulant Graphs.
IEEE Trans. Inf. Theory, 2007

Perfect Codes over Lipschitz Integers.
Proceedings of the IEEE International Symposium on Information Theory, 2007

Mixed-radix Twisted Torus Interconnection Networks.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Implicit Transactional Memory in Kilo-Instruction Multiprocessors.
Proceedings of the Advances in Computer Systems Architecture, 2007

2006
High-performance adaptive routing for networks with arbitrary topology.
J. Syst. Archit., 2006

Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors.
Int. J. Parallel Program., 2006

A Generalization of Perfect Lee Codes over Gaussian Integers.
Proceedings of the Proceedings 2006 IEEE International Symposium on Information Theory, 2006

2005
Practicable Layouts for Optimal Circulant Graphs.
Proceedings of the 13th Euromicro Workshop on Parallel, 2005

On the perfect t-dominating set problem in circulant graphs and codes over gaussian integers.
Proceedings of the 2005 IEEE International Symposium on Information Theory, 2005

Implementing Kilo-Instruction Multiprocessors.
Proceedings of the International Conference on Pervasive Services 2005, 2005

On Finding a Shortest Path in Circulant Graphs with Two Jumps.
Proceedings of the Computing and Combinatorics, 11th Annual International Conference, 2005

2004
Evaluating kilo-instruction multiprocessors.
Proceedings of the 3rd Workshop on Memory Performance Issues, 2004

Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

Load Unbalance in k-ary n-Cube Networks.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

Understanding Buffer Management for Cut-Through 1D Rings.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

A first glance at Kilo-instruction based multiprocessors.
Proceedings of the First Conference on Computing Frontiers, 2004

2003
On the Design of a High-Performance Adaptive Router for CC-NUMA Multiprocessors.
IEEE Trans. Parallel Distributed Syst., 2003

Distance-Hereditary Embeddings of Circulant Graphs.
Proceedings of the 2003 International Symposium on Information Technology (ITCC 2003), 2003

Chordal Topologies for Interconnection Networks.
Proceedings of the High Performance Computing, 5th International Symposium, 2003

A Low Cost Fault Tolerant Packet Routing for Parallel Computers.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
Modeling of interconnection subsystems for massively parallel computers.
Perform. Evaluation, 2002

SICOSYS: An Integrated Framework for studying Interconnection Network Performance in Multiprocessor Systems.
Proceedings of the 10th Euromicro Workshop on Parallel, 2002

2001
The Adaptive Bubble Router.
J. Parallel Distributed Comput., 2001

A Comparison of Router Architectures for Virtual Cut-Through and Wormhole Switching in a NOW Environment.
J. Parallel Distributed Comput., 2001

A new routing mechanism for networks with irregular topology.
Proceedings of the 2001 ACM/IEEE conference on Supercomputing, 2001

A New Communication Mechanism for Cluster Computing.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001

Topic 12: Routing and Communication in Interconnection Networks.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001

2000
A case study of trace-driven simulation for analyzing interconnection networks: cc-NUMAs with ILP processors.
Proceedings of the Eight Euromicro Workshop on Parallel and Distributed Processing, 2000

Pipelining Router Design Improves Parallel System Performance.
Proceedings of the 5th International Symposium on Parallel Architectures, 2000

Improving parallel system performance by changing the arrangement of the network links.
Proceedings of the 14th international conference on Supercomputing, 2000

1999
Performance evaluation of the bubble algorithm: benefits for k-ary n-cubes.
Proceedings of the Seventh Euromicro Workshop on Parallel and Distributed Processing. PDP'99, 1999

A Comparison of Router Architectures for Virtual Cut-Through and Wormhole Switching in a NOWEnvironment.
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999

Low-level router design and its impact on supercomputer system performance.
Proceedings of the 13th international conference on Supercomputing, 1999

Adaptive Bubble Router: A Design to Improve Performance in Torus Networks.
Proceedings of the International Conference on Parallel Processing 1999, 1999

Impact of the Head-of-Line Blocking on Parallel Computer Networks: Hardware to Applications.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998
An evaluation of implementations of the CMB parallel simulation algorithm on distributed memory multicomputers.
J. Syst. Archit., 1998

Ghost packets: a deadlock-free solution for k-ary n-cube networks.
Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing, 1998

1997
A flow control mechanism to avoid message deadlock in k-ary n-cube networks.
Proceedings of the Fourth International on High-Performance Computing, 1997

1996
Assessing the Performance of the New IBM SP2 Communication Subsystem.
IEEE Parallel Distributed Technol. Syst. Appl., 1996

An Empirical Evaluation of Techniques for Parallel Discrete-Event Simulation of Interconnection Networks.
Proceedings of the 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996

1995
Parallel simulation of message routing networks.
Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), 1995

Petri Net Modeling of Interconnection Networks for Massively Parallel Architectures.
Proceedings of the 9th international conference on Supercomputing, 1995

1994
Mad-postman : A Look-ahead Message Propagation Method For Static Bidimensional Meshes.
Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994

1993
A Perfomance Evaluation of Adaptive Routing in Bidimensional Cut-Through Networks.
Parallel Process. Lett., 1993

Experimental evaluation of Mad Postman bidimensional routing networks.
Microprocess. Microprogramming, 1993

1992
Analysis and evaluation of message management functions for bidimensional transputer networks.
Microprocess. Microsystems, 1992

1991
Optimal Distance Networks of Low Degree for Parallel Computers.
IEEE Trans. Computers, 1991

1987
Optimized Mesh-Connected Networks for SIMD and MIMD Architectures.
Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987


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