Eric Belhaire

According to our database, Eric Belhaire authored at least 9 papers between 1988 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2009

TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA.

Weisheng Zhao, Eric Belhaire, Claude Chappert, Bernard Dieny, Guillaume Prenat

ACM Trans. Reconfigurable Technol. Syst., 2009

Spin transfer torque (STT)-MRAM-based runtime reconfiguration FPGA circuit.

Weisheng Zhao, Eric Belhaire, Claude Chappert, Pascale Mazoyer

ACM Trans. Embed. Comput. Syst., 2009

2008

Spintronic Device Based Non-volatile Low Standby Power SRAM.

Weisheng Zhao, Eric Belhaire, Claude Chappert, Pascale Mazoyer

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007

Synthesis of Finite State Machines with Magnetic Domain Wall Logic.

Jacques-Olivier Klein, Eric Belhaire, Claude Chappert, Florent Ouchet, Russell Cowburn, Dan Read, Dorothee Petit

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

CMOS/Magnetic Hybrid Architectures.

Guillaume Prenat, Mourad El Baraji, Wei Guo, Ricardo Sousa, Liliana Buda-Prejbeanu, Bernard Dieny, Virgile Javerliac, Jean-Pierre Nozieres, Weisheng Zhao, Eric Belhaire

Proceedings of the 14th IEEE International Conference on Electronics, 2007

TAS-MRAM based Non-volatile FPGA logic circuit.

Weisheng Zhao, Eric Belhaire, Bernard Dieny, Guillaume Prenat, Claude Chappert

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

2001

Fast, Minimal Decoding Complexity, System Level, Binary Systematic (41, 32) Single-Error-Correcting Codes for On-Chip DRAM Applications.

Amir Kazéminéjad, Eric Belhaire

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

1996

An optoelectronic CMOS circuit implementing a simulated annealing algorithm.

Antoine Dupret, Eric Belhaire, Jean-Claude Rodier, Philippe Lalanne, Donald PrCvost, Patrick Garda, Pierre Chavel

IEEE J. Solid State Circuits, 1996

1988

A 60x60 Processor Array Smart Sensor for Binary Image Processung.

A. Reichart, Patrick Garda, Eric Belhaire, Francis J. Devos, Bertrand Y. Zavidovique

Proceedings of IAPR Workshop on Computer Vision, 1988