Jacques-Olivier Klein

Orcid: 0000-0002-6923-5276

According to our database1, Jacques-Olivier Klein authored at least 85 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Improving Normalizing Flows with the Approximate Mass for Out-of-Distribution Detection.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

2021
Implementation of Ternary Weights With Resistive RAM Using a Single Sense Operation Per Synapse.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks.
CoRR, 2021

2020
Embracing the Unreliability of Memory Devices for Neuromorphic Computing.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
Ultra-Dense Ring-Shaped Racetrack Memory Cache Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A comprehensive compact model for the design of all-spin-logic based circuits.
Microelectron. J., 2019

Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays.
CoRR, 2019

In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks.
CoRR, 2019

Stochastic Computing for Hardware Implementation of Binarized Neural Networks.
IEEE Access, 2019

Contrasting Advantages of Learning With Random Weights and Backpropagation in Non-Volatile Memory Neural Networks.
IEEE Access, 2019

Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Memory-Centric Neuromorphic Computing With Nanodevices.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
Multiscaled Simulation Methodology for Neuro-Inspired Circuits Demonstrated with an Organic Memristor.
IEEE Trans. Multi Scale Comput. Syst., 2018

Large scale, high density integration of all spin logic.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Arithmetic Logic Unit based on all-spin logic devices.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Spatio-temporal learning with arrays of analog nanosynapses.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Offset Analysis and Design Optimization of a Dynamic Sense Amplifier for Resistive Memories.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

All Spin Artificial Neural Networks Based on Compound Spintronic Synapse and Neuron.
IEEE Trans. Biomed. Circuits Syst., 2016

A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI.
Microelectron. Reliab., 2016

Read disturbance issue and design techniques for nanoscale STT-MRAM.
J. Syst. Archit., 2016

Stochastic spintronic device based synapses and spiking neurons for neuromorphic computation.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

A novel circuit design of true random number generator using magnetic tunnel junction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Exploiting the short-term to long-term plasticity transition in memristive nanodevice learning architectures.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

A recurrent crossbar of memristive nanodevices implements online novelty detection.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016

2015
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Spin-Transfer Torque Magnetic Memory as a Stochastic Memristive Synapse for Neuromorphic Systems.
IEEE Trans. Biomed. Circuits Syst., 2015

Compact thermal modeling of spin transfer torque magnetic tunnel junction.
Microelectron. Reliab., 2015

Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology.
ACM J. Emerg. Technol. Comput. Syst., 2015

On-Chip Universal Supervised Learning Methods for Neuro-Inspired Block of Memristive Nanodevices.
ACM J. Emerg. Technol. Comput. Syst., 2015

Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Read disturbance issue for nanoscale STT-MRAM.
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Robust magnetic full-adder with voltage sensing 2T/2MTJ cell.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Supervised learning with organic memristor devices and prospects for neural crossbar arrays.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Full-adder circuit design based on all-spin logic device.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Perspectives of racetrack memory based on current-induced domain wall motion: From device to system.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Vortex-based spin transfer oscillator compact model for IC design.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

From device to system: cross-layer design exploration of racetrack memory.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Spintronic devices as key elements for energy-efficient neuroinspired architectures.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses.
Microelectron. Reliab., 2014

Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.
J. Parallel Distributed Comput., 2014

Robust learning approach for neuro-inspired nanoscale crossbar architecture.
ACM J. Emerg. Technol. Comput. Syst., 2014

One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories.
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014

Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Sneak paths effects in CBRAM memristive devices arrays for spiking neural networks.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

On-chip supervised learning rule for ultra high density neural crossbar using memristor for synapse and neuron.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Spin-transfer torque magnetic memory as a stochastic memristive synapse.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Ferroelectric tunnel memristor-based neuromorphic network with 1T1R crossbar architecture.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

Spintronics for low-power computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

An overview of spin-based integrated circuits.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Magnetic Adder Based on Racetrack Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A low-cost built-in error correction circuit design for STT-MRAM reliability improvement.
Microelectron. Reliab., 2013

Spin-electronics based logic fabrics.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Emerging hybrid logic circuits based on non-volatile magnetic memories.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Synchronous full-adder based on complementary resistive switching memory cells.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Low power magnetic flip-flop based on checkpointing and self-enable mechanism.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Analytical study of complementary memristive synchronous logic gates.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Design study of efficient digital order-based STDP neuron implementations for extracting temporal features.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

2012
Failure and reliability analysis of STT-MRAM.
Microelectron. Reliab., 2012

Cross-point architecture for spin transfer torque magnetic random access memory
CoRR, 2012

Crossbar architecture based on 2R complementary resistive switching memory cell.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Bioinspired networks with nanoscale memristive devices that combine the unsupervised and supervised learning approaches.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Nanodevice-based novel computing paradigms and the neuromorphic approach.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

MRAM crossbar based configurable logic block.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Design and Modeling of a Neuro-Inspired Learning Circuit Using Nanotube-Based Memory Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Design considerations and strategies for high-reliable STT-MRAM.
Microelectron. Reliab., 2011

Embedded MRAM for high-speed computing.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

High Performance SoC Design Using Magnetic Logic and Memory.
Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011

Robust neural logic block (NLB) based on memristor crossbar array.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Design of MRAM based logic circuits and its applications.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Design of embedded MRAM macros for memory-in-logic applications.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

High Density Asynchronous LUT Based on Non-volatile MRAM Technology.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2008
A Smart Architecture for Low-Level Image Computing.
Int. J. Comput. Sci. Appl., 2008

2007
Image Processing Vision Systems: Standard Image Sensors Versus Retinas.
IEEE Trans. Instrum. Meas., 2007

Synthesis of Finite State Machines with Magnetic Domain Wall Logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005
Low Power Image Processing: Analog Versus Digital Comparison.
Proceedings of the Seventh International Workshop on Computer Architectures for Machine Perception (CAMP 2005), 2005

2004
An improved analog computation cell for Paris II, a programmable vision chip.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2002
A DSP-like analogue processing unit for smart image sensors.
Int. J. Circuit Theory Appl., 2002


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