Virgile Javerliac

According to our database, Virgile Javerliac authored at least 4 papers between 2007 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories.

Christophe Layer, Laurent Becker, Kotb Jabeur, Sylvain Claireux, Bernard Dieny, Guillaume Prenat, Gregory di Pendina, Stephane Gros, Pierre Paoli, Virgile Javerliac, Fabrice Bernard-Granger, Loïc Decloedt

ACM J. Emerg. Technol. Comput. Syst., 2016

2015

Low-power hybrid STT/CMOS system-on-chip embedding non-volatile magnetic memory blocks.

Christophe Layer, Kotb Jabeur, Stephane Gros, Laurent Becker, Pierre Paoli, Fabrice Bernard-Granger, Virgile Javerliac, Bernard Dieny

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Hybrid STT/CMOS Design of an Interrupt Based Instant On/Off Mechanism for Low-Power SoC.

Christophe Layer, Kotb Jabeur, Laurent Becker, Bernard Dieny, Stephane Gros, Virgile Javerliac, Pierre Paoli, Fabrice Bernard-Granger

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2007

CMOS/Magnetic Hybrid Architectures.

Guillaume Prenat, Mourad El Baraji, Wei Guo, Ricardo Sousa, Liliana Buda-Prejbeanu, Bernard Dieny, Virgile Javerliac, Jean-Pierre Nozieres, Weisheng Zhao, Eric Belhaire

Proceedings of the 14th IEEE International Conference on Electronics, 2007