Weisheng Zhao

According to our database1, Weisheng Zhao authored at least 143 papers between 2007 and 2019.

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Bibliography

2019
Ultra-Dense Ring-Shaped Racetrack Memory Cache Design.
IEEE Trans. on Circuits and Systems, 2019

Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration.
IEEE Trans. on Circuits and Systems, 2019

Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Low-Power (1T1N) Skyrmionic Synapses for Spiking Neuromorphic Systems.
IEEE Access, 2019

2018
A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT.
IEEE Trans. on Circuits and Systems, 2018

Design and Fabrication of Full Wheatstone-Bridge-Based Angular GMR Sensors.
Sensors, 2018

Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint.
J. Comput. Sci. Technol., 2018

Upper bounds on the bondage number of the strong product of a graph and a tree.
Int. J. Comput. Math., 2018

Matchings extend to Hamiltonian cycles in 5-cube.
Discussiones Mathematicae Graph Theory, 2018

A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM.
IEEE Access, 2018

A Comparative Study on Racetrack Memories: Domain Wall vs. Skyrmion.
Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018

Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Emerging Neuromorphic Computing Paradigms Exploring Magnetic Skyrmions.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

MRAM-on-FDSOI Integration: A Bit-Cell Perspective.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Radiation hardening design for spin-orbit torque magnetic random access memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Progresses and challenges of spin orbit torque driven magnetization switching and application (Invited).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

NEAR: A Novel Energy Aware Replacement Policy for STT-MRAM LLCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Data Management for Magnetic Racetrack Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Magnetic skyrmions for future potential memory and logic applications: Alternative information carriers.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Spintronics based stochastic computing for efficient Bayesian inference system.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Process variation aware data management for magnetic skyrmions racetrack memory.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

High-Density and Fast-Configuration Non-Volatile Look-Up Table Based on NAND-Like Spintronic Memory.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

A Novel 15T-4MTJ based Non-volatile Ternary Content-Addressable Memory Cell for High-Speed, Low-Power and High-Reliable Search Operation.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Dynamic Dual-Reference Sensing Scheme for Deep Submicrometer STT-MRAM.
IEEE Trans. on Circuits and Systems, 2017

Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology.
IEEE Trans. on Circuits and Systems, 2017

Pseudo-Differential Sensing Framework for STT-MRAM: A Cross-Layer Perspective.
IEEE Trans. Computers, 2017

Bondage number of the strong product of two trees.
Discrete Applied Mathematics, 2017

Interfacial property tuning of heavy metal/CoFeB for large density STT-MRAM.
Proceedings of the 17th Non-Volatile Memory Technology Symposium, 2017

Arithmetic Logic Unit based on all-spin logic devices.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Frequency modulation of spin torque nano oscillator with voltage controlled magnetic anisotropy effect.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Proposal for novel magnetic memory device with spin momentum locking materials.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Reconfigurable processing in memory architecture based on spin orbit torque.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Programmable Stateful In-Memory Computing Paradigm via a Single Resistive Device.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

PRESCOTT: Preset-based cross-point architecture for spin-orbit-torque magnetic random access memory.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Advanced Low Power Spintronic Memories beyond STT-MRAM.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

A true random number generator based on parallel STT-MTJs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Voltage-controlled MRAM for working memory: Perspectives and challenges.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Ultrafast spintronic integrated circuits.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect.
IEEE Trans. VLSI Syst., 2016

Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM.
IEEE Trans. Reliability, 2016

Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.
IEEE Trans. on Circuits and Systems, 2016

Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

All Spin Artificial Neural Networks Based on Compound Spintronic Synapse and Neuron.
IEEE Trans. Biomed. Circuits and Systems, 2016

Skyrmion-Electronics: An Overview and Outlook.
Proceedings of the IEEE, 2016

A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI.
Microelectronics Reliability, 2016

Read disturbance issue and design techniques for nanoscale STT-MRAM.
Journal of Systems Architecture - Embedded Systems Design, 2016

The bondage number of the strong product of a complete graph with a path and a special starlike tree.
Discrete Math., Alg. and Appl., 2016

Stochastic spintronic device based synapses and spiking neurons for neuromorphic computation.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Ultra-low power all spin logic device acceleration based on voltage controlled magnetic anisotropy.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

A novel circuit design of true random number generator using magnetic tunnel junction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

A spin Hall effect-based multi-level cell for MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Multi-context non-volatile content addressable memory using magnetic tunnel junctions.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Evaluation of spin-Hall-assisted STT-MRAM for cache replacement.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Approximate computing in MOS/spintronic non-volatile full-adder.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Quantitative evaluation of reliability and performance for STT-MRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Spin wave based synapse and neuron for ultra low power neuromorphic computation system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

PDS: pseudo-differential sensing scheme for STT-MRAM.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Guest Editorial for Special Issue on Emerging Memory Technologies - Modeling, Design, and Applications for Multi-Scale Computing.
IEEE Trans. Multi-Scale Computing Systems, 2015

Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction.
IEEE Trans. on Circuits and Systems, 2015

Spin-Transfer Torque Magnetic Memory as a Stochastic Memristive Synapse for Neuromorphic Systems.
IEEE Trans. Biomed. Circuits and Systems, 2015

Compact thermal modeling of spin transfer torque magnetic tunnel junction.
Microelectronics Reliability, 2015

Tunnel Junction with Perpendicular Magnetic Anisotropy: Status and Challenges.
Micromachines, 2015

Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology.
JETC, 2015

On-Chip Universal Supervised Learning Methods for Neuro-Inspired Block of Memristive Nanodevices.
JETC, 2015

Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

On restricted edge connectivity of strong product graphs.
Ars Comb., 2015

Realization of neural coding by stochastic switching of magnetic tunnel junction.
Proceedings of the 2015 15th Non-Volatile Memory Technology Symposium (NVMTS), 2015

Nonvolatile radiation hardened DICE latch.
Proceedings of the 2015 15th Non-Volatile Memory Technology Symposium (NVMTS), 2015

Read disturbance issue for nanoscale STT-MRAM.
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

An architecture-level cache simulation framework supporting advanced PMA STT-MRAM.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Robust magnetic full-adder with voltage sensing 2T/2MTJ cell.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Full-adder circuit design based on all-spin logic device.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Energy-efficient neuromorphic computation based on compound spin synapse with stochastic learning.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Perspectives of racetrack memory based on current-induced domain wall motion: From device to system.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A body-biasing of readout circuit for STT-RAM with improved thermal reliability.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Vortex-based spin transfer oscillator compact model for IC design.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A new self-reference sensing scheme for TLC MRAM.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Hi-fi playback: tolerating position errors in shift operations of racetrack memory.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

From device to system: cross-layer design exploration of racetrack memory.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Spintronic devices as key elements for energy-efficient neuroinspired architectures.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Recent progresses of STT memory design and applications.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Spin orbit torques for ultra-low power computing.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories.
IEEE Trans. on Circuits and Systems, 2014

Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms.
IEEE Trans. on Circuits and Systems, 2014

Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses.
Microelectronics Reliability, 2014

Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.
J. Parallel Distrib. Comput., 2014

Robust learning approach for neuro-inspired nanoscale crossbar architecture.
JETC, 2014

On restricted edge-connectivity of lexicographic product graphs.
Int. J. Comput. Math., 2014

One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories.
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014

Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

On-chip supervised learning rule for ultra high density neural crossbar using memristor for synapse and neuron.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Spin-transfer torque magnetic memory as a stochastic memristive synapse.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Ferroelectric tunnel memristor-based neuromorphic network with 1T1R crossbar architecture.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

Spintronics for low-power computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

An overview of spin-based integrated circuits.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Magnetic Adder Based on Racetrack Memory.
IEEE Trans. on Circuits and Systems, 2013

Pavlov's Dog Associative Learning Demonstrated on Synaptic-Like Organic Transistors.
Neural Computation, 2013

A low-cost built-in error correction circuit design for STT-MRAM reliability improvement.
Microelectronics Reliability, 2013

Design and analysis of the reference cells for STT-MRAM.
IEICE Electronic Express, 2013

Spin-electronics based logic fabrics.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Emerging hybrid logic circuits based on non-volatile magnetic memories.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Synchronous full-adder based on complementary resistive switching memory cells.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Low power magnetic flip-flop based on checkpointing and self-enable mechanism.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Analytical study of complementary memristive synchronous logic gates.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

2012
Failure and reliability analysis of STT-MRAM.
Microelectronics Reliability, 2012

Crossbar architecture based on 2R complementary resistive switching memory cell.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Bioinspired networks with nanoscale memristive devices that combine the unsupervised and supervised learning approaches.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Nanodevice-based novel computing paradigms and the neuromorphic approach.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

MRAM crossbar based configurable logic block.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Design and Modeling of a Neuro-Inspired Learning Circuit Using Nanotube-Based Memory Devices.
IEEE Trans. on Circuits and Systems, 2011

Design considerations and strategies for high-reliable STT-MRAM.
Microelectronics Reliability, 2011

Embedded MRAM for high-speed computing.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

High Performance SoC Design Using Magnetic Logic and Memory.
Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011

Robust neural logic block (NLB) based on memristor crossbar array.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Design of MRAM based logic circuits and its applications.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Magnetic memory (MRAM), a new area for 2D and 3D SoC/SiP design.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Development of a functional model for the Nanoparticle-Organic Memory transistor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Carbon nanotube-based programmable devices for adaptive architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Design of embedded MRAM macros for memory-in-logic applications.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

High Density Asynchronous LUT Based on Non-volatile MRAM Technology.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA.
TRETS, 2009

Spin transfer torque (STT)-MRAM-based runtime reconfiguration FPGA circuit.
ACM Trans. Embedded Comput. Syst., 2009

Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design.
Proceedings of the Nano-Net - 4th International ICST Conference, 2009

Nanocomputing Block based Multi-Context FPGA.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

2008
Spintronic Device Based Non-volatile Low Standby Power SRAM.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007
CMOS/Magnetic Hybrid Architectures.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

TAS-MRAM based Non-volatile FPGA logic circuit.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007


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