Weisheng Zhao
Orcid: 0000-0001-8088-0404
According to our database1,
Weisheng Zhao
authored at least 272 papers
between 2007 and 2024.
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Bibliography
2024
A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
Area and Energy Efficient Short-Circuit-Logic-Based STT-MRAM Crossbar Array for Binary Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024
CIMQ: A Hardware-Efficient Quantization Framework for Computing-In-Memory-Based Neural Network Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024
2023
IMGA: Efficient In-Memory Graph Convolution Network Aggregation With Data Flow Optimizations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
Proximity-induced magnetic order in topological insulator on ferromagnetic semiconductor.
Sci. China Inf. Sci., December, 2023
Sci. China Inf. Sci., June, 2023
Implementation of 16 Boolean logic operations based on one basic cell of spin-transfer-torque magnetic random access memory.
Sci. China Inf. Sci., June, 2023
Layout Aware Optimization Methodology for SOT-MRAM Based on Technically Feasible Top-Pinned Magnetic Tunnel Junction Process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023
NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration.
Sci. China Inf. Sci., April, 2023
ACM Trans. Design Autom. Electr. Syst., March, 2023
Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies.
ACM Trans. Embed. Comput. Syst., March, 2023
Perpendicular magnetic anisotropy based spintronics devices in Pt/Co stacks under different hard and flexible substrates.
Sci. China Inf. Sci., February, 2023
IEEE Trans. Emerg. Top. Comput., 2023
Full reliability characterization of three-terminal SOT-MTJ devices and corresponding arrays.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
THE-V: Verifiable Privacy-Preserving Neural Network via Trusted Homomorphic Execution.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
TAM: A Computing in Memory based on Tandem Array within STT-MRAM for Energy-Efficient Analog MAC Operation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Toward Energy-Efficient Sparse Matrix-Vector Multiplication with near STT-MRAM Computing Architecture.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Machine Learning Attack-Resilient Strong PUF Leveraging the Process Variation of MRAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Accelerating Graph-Connected Component Computation With Emerging Processing-In-Memory Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
S<sup>2</sup> Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks.
IEEE Trans. Computers, 2022
IEEE Trans. Computers, 2022
J. Graph Theory, 2022
Distributed Parallel Databases, 2022
Femtosecond laser-assisted switching in perpendicular magnetic tunnel junctions with double-interface free layer.
Sci. China Inf. Sci., 2022
Sci. China Inf. Sci., 2022
An In-memory Booth Multiplier Based on Non-volatile Memory for Neural Network Applications.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
CP-SRAM: charge-pulsation SRAM marco for ultra-high energy-efficiency computing-in-memory.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Work-in-Progress: Toward Energy-efficient Near STT-MRAM Processing Architecture for Neural Networks.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2022
Proceedings of the Approximate Computing, 2022
2021
Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization.
IEEE Trans. Neural Networks Learn. Syst., 2021
Proposal of High Density Two-Bits-Cell Based NAND-Like Magnetic Random Access Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Proc. IEEE, 2021
Mob. Inf. Syst., 2021
Forecasting the outcome of spintronic experiments with Neural Ordinary Differential Equations.
CoRR, 2021
CoRR, 2021
CoRR, 2021
Complex., 2021
Sci. China Inf. Sci., 2021
Tuning the pinning direction of giant magnetoresistive sensor by post annealing process.
Sci. China Inf. Sci., 2021
Brief Industry Paper: optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms.
Proceedings of the 27th IEEE Real-Time and Embedded Technology and Applications Symposium, 2021
A Novel Multi-Context Non-Volatile Content-Addressable Memory Cell and Multi-Level Architecture for High Reliability and Density.
Proceedings of the 10th IEEE Non-Volatile Memory Systems and Applications Symposium, 2021
Multi-order Nonlinearities and Resulting Coherent Oscillations of the States in Quantum Dot-Mechanical Resonator Hybrid System.
Proceedings of the 16th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2021
A Computing-in-memory Scheme with Series Bit-cell in STT-MRAM for Efficient Multi-bit Analog Multiplication.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
Soft Error Sensitivity of Magnetic Random Access Memory and Its Radiation Hardening Design.
Proceedings of the 18th International SoC Design Conference, 2021
Fully Single Event Double Node Upset Tolerant Design for Magnetic Random Access Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Computing-in-Memory Paradigm Based on STT-MRAM with Synergetic Read/Write-Like Modes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
SpinSim: A Computer Architecture-Level Variation Aware STT-MRAM Performance Evaluation Framework.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
SpinLiM: Spin Orbit Torque Memory for Ternary Neural Networks Based on the Logic-in-Memory Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
FedSkel: Efficient Federated Learning on Heterogeneous Systems with Skeleton Gradients Update.
Proceedings of the CIKM '21: The 30th ACM International Conference on Information and Knowledge Management, Virtual Event, Queensland, Australia, November 1, 2021
Tiny neural network search and implementation for embedded FPGA: a software-hardware co-design approach.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing.
IEEE Trans. Circuits Syst., 2020
Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Design of Magnetic Non-Volatile TCAM With Priority-Decision in Memory Technology for High Speed, Low Power, and High Reliability.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Magnetic Cell Centrifuge Platform Performance Study with Different Microsieve Pore Geometries.
Sensors, 2020
Hardware Security in Spin-based Computing-in-memory: Analysis, Exploits, and Mitigation Techniques.
ACM J. Emerg. Technol. Comput. Syst., 2020
Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization.
ACM J. Emerg. Technol. Comput. Syst., 2020
ACM J. Emerg. Technol. Comput. Syst., 2020
Frontiers Comput. Sci., 2020
An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing.
CCF Trans. High Perform. Comput., 2020
Compact Modeling and Analysis of Voltage-Gated Spin-Orbit Torque Magnetic Tunnel Junction.
IEEE Access, 2020
A Diode-Enhanced Scheme for Giant Magnetoresistance Amplification and Reconfigurable Logic.
IEEE Access, 2020
Movable-Type Transfer and Stacking of van der Waals Heterostructures for Spintronics.
IEEE Access, 2020
Voltage-Gated Spin-Hall Effect Based Magnetic Non-Volatile Flip-Flop for High Speed, Low Power and Compact Cell Area.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Computing-in-Memory Architecture Based on Field-Free SOT-MRAM with Self-Reference Method.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
PRISM: Energy-Efficient Polymorphic Operation Based on Spin-Orbit Torque Memory for Reconfigurable Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
An In-memory Highly Reconfigurable Logic Circuit Based on Diode-assisted Enhanced Magnetoresistance Device.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
High-Density, Low-Power Voltage-Control Spin Orbit Torque Memory with Synchronous Two-Step Write and Symmetric Read Techniques.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2019
DASM: Data-Streaming-Based Computing in Nonvolatile Memory Architecture for Embedded System.
IEEE Trans. Very Large Scale Integr. Syst., 2019
J. Supercomput., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A Novel MTJ-Based Non-Volatile Ternary Content-Addressable Memory for High-Speed, Low-Power, and High-Reliable Search Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Novel Radiation Hardening Read/Write Circuits Using Feedback Connections for Spin-Orbit Torque Magnetic Random Access Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Computers, 2019
Efficient technique for <i>ab-initio</i> calculation of magnetocrystalline anisotropy energy.
Comput. Phys. Commun., 2019
Erase-hidden and Drivability-improved Magnetic Non-Volatile Flip-Flops with NAND-SPIN Devices.
CoRR, 2019
Multi-Port 1R1W Transpose Magnetic Random Access Memory by Hierarchical Bit-Line Switching.
IEEE Access, 2019
IEEE Access, 2019
Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Ultra-fast and Energy-efficient Write-Computing Operation for Neuromorphic Computing.
Proceedings of the 2019 International SoC Design Conference, 2019
Modulation and Demodulation of Digital Frequency Shift Keying System Based on Spin Torque Nano Oscillator with Voltage Controlled Magnetic Anisotropy Effect.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Skyrmion Racetrack Memory based Computing In-memory Architecture for Binary Neural Convolutional Network.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
ZUMA: Enabling Direct Insertion/Deletion Operations with Emerging Skyrmion Racetrack Memory.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Sensors, 2018
Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint.
J. Comput. Sci. Technol., 2018
Int. J. Comput. Math. Comput. Syst. Theory, 2018
Int. J. Comput. Math., 2018
Construction for Trees without vertices contained in all minimum dominating sets.
Ars Comb., 2018
IEEE Access, 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018
Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Progresses and challenges of spin orbit torque driven magnetization switching and application (Invited).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform.
Proceedings of the International Conference on Field-Programmable Technology, 2018
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
Magnetic skyrmions for future potential memory and logic applications: Alternative information carriers.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
High-Density and Fast-Configuration Non-Volatile Look-Up Table Based on NAND-Like Spintronic Memory.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
A Novel 15T-4MTJ based Non-volatile Ternary Content-Addressable Memory Cell for High-Speed, Low-Power and High-Reliable Search Operation.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Trans. Computers, 2017
Proceedings of the 17th Non-Volatile Memory Technology Symposium, 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Frequency modulation of spin torque nano oscillator with voltage controlled magnetic anisotropy effect.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
PRESCOTT: Preset-based cross-point architecture for spin-orbit-torque magnetic random access memory.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Reliab., 2016
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Trans. Biomed. Circuits Syst., 2016
A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI.
Microelectron. Reliab., 2016
J. Syst. Archit., 2016
The bondage number of the strong product of a complete graph with a path and a special starlike tree.
Discret. Math. Algorithms Appl., 2016
Skyrmions as Compact, Robust and Energy-Efficient Interconnects for Domain Wall (DW)-based Systems.
CoRR, 2016
Stochastic spintronic device based synapses and spiking neurons for neuromorphic computation.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Ultra-low power all spin logic device acceleration based on voltage controlled magnetic anisotropy.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
A novel circuit design of true random number generator using magnetic tunnel junction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Multi-context non-volatile content addressable memory using magnetic tunnel junctions.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Spin wave based synapse and neuron for ultra low power neuromorphic computation system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Guest Editorial for Special Issue on Emerging Memory Technologies - Modeling, Design, and Applications for Multi-Scale Computing.
IEEE Trans. Multi Scale Comput. Syst., 2015
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Spin-Transfer Torque Magnetic Memory as a Stochastic Memristive Synapse for Neuromorphic Systems.
IEEE Trans. Biomed. Circuits Syst., 2015
Microelectron. Reliab., 2015
Micromachines, 2015
ACM J. Emerg. Technol. Comput. Syst., 2015
On-Chip Universal Supervised Learning Methods for Neuro-Inspired Block of Memristive Nanodevices.
ACM J. Emerg. Technol. Comput. Syst., 2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
On restricted edge connectivity of strong product graphs.
Ars Comb., 2015
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Energy-efficient neuromorphic computation based on compound spin synapse with stochastic learning.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Perspectives of racetrack memory based on current-induced domain wall motion: From device to system.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses.
Microelectron. Reliab., 2014
Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.
J. Parallel Distributed Comput., 2014
ACM J. Emerg. Technol. Comput. Syst., 2014
Int. J. Comput. Math., 2014
One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories.
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014
Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
On-chip supervised learning rule for ultra high density neural crossbar using memristor for synapse and neuron.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Ferroelectric tunnel memristor-based neuromorphic network with 1T1R crossbar architecture.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Neural Comput., 2013
A low-cost built-in error correction circuit design for STT-MRAM reliability improvement.
Microelectron. Reliab., 2013
IEICE Electron. Express, 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
2012
CoRR, 2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Bioinspired networks with nanoscale memristive devices that combine the unsupervised and supervised learning approaches.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Design and Modeling of a Neuro-Inspired Learning Circuit Using Nanotube-Based Memory Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Microelectron. Reliab., 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
2009
ACM Trans. Reconfigurable Technol. Syst., 2009
ACM Trans. Embed. Comput. Syst., 2009
Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design.
Proceedings of the Nano-Net - 4th International ICST Conference, 2009
Nanocomputing Block based Multi-Context FPGA.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007