Eslam Yahya

According to our database1, Eslam Yahya authored at least 21 papers between 2003 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2018
A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017
130nm Low power asynchronous AES core.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Power efficient AES core for IoT constrained devices implemented in 130nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
ERSUT: A Self-Healing Architecture for Mitigating PVT Variations Without Pipeline Flushing.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Accuracy-improved coupling capacitance model for through-silicon via (TSV) arrays using dimensional analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Presenting a synchronous - Asynchronous standard cell library based on 7nm FinFET technology.
Proceedings of the 28th International Conference on Microelectronics, 2016

2015
Library based macro-modeling methodology for Through Silicon Via (TSV) arbitrary arrays.
Microelectron. J., 2015

Deadlock detection in conditional asynchronous circuits under mismatched branch selection.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Coupling capacitance extraction in through-silicon via (TSV) arrays.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Different scenarios for estimating coupling capacitances of through silicon via (TSV) arrays.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015

2013
Variability mitigation using correction function technique.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

2010
A high-speed high-resolution low-phase noise oscillator using self-timed rings.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks.
Proceedings of the VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 2010

Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

2009
Asynchronous design: A promising paradigm for electronic circuits and systems.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Programmable/Stoppable Oscillator Based on Self-Timed Rings.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

2008
Asynchronous Linear Pipelines: An efficient-optimal pipelining algorithm.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Performance Modeling and Analysis of Asynchronous Linear-Pipeline with Time Variable Delays.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

2003
Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003


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