François Charot

According to our database1, François Charot
  • authored at least 34 papers between 1986 and 2013.
  • has a "Dijkstra number"2 of four.

Timeline

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Bibliography

2013
GeCoS: A framework for prototyping custom hardware design flows.
Proceedings of the 13th IEEE International Working Conference on Source Code Analysis and Manipulation, 2013

2012
Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation.
TRETS, 2012

Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture.
IJERTCS, 2012

2011
Exploiting reconfigurable SWP operators for multimedia applications.
Proceedings of the IEEE International Conference on Acoustics, 2011

2010
Energy efficient sensor node implementations.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Design Methodology for a High Performance Robust DVB-S2 Decoder Implementation.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2009
Constraint-Driven Identification of Application Specific Instructions in the DURASE System.
Proceedings of the Embedded Computer Systems: Architectures, 2009

How Constrains Programming Can Help You in the Generation of Optimized Application Specific Reconfigurable Processor Extensions.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Architecture-Driven Synthesis of Reconfigurable Cells.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

A generic architecture of CCSDS Low Density Parity Check decoder for near-earth applications.
Proceedings of the Design, Automation and Test in Europe, 2009

Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008
A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

A New High Performance Multi Gigabit String Matching Engine.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

A Parallel and Modular Architecture for 802.16e LDPC Codes.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2006
A Programmable, Maximal Throughput Architecture for Neighborhood Image Processing.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image Processing.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2004
Architecture Exploration for 3G Telephony Applications Using a Hardware-Software Prototyping Platform.
Proceedings of the Computer Systems: Architectures, 2004

Proposal of a Parallel Architecture for a Motion Detection Algorithm.
Proceedings of the 17th International Conference on Pattern Recognition, 2004

FPGA Implementation of a Vision-Based Motion Estimation Algorithm for an Underwater Robot.
Proceedings of the Field Programmable Logic and Application, 2004

Modeling and Scheduling Parallel Data Flow Systems using Structured Systems of Recurrence Equations.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
Automatic floating-point to fixed-point conversion for DSP code generation.
Proceedings of the International Conference on Compilers, 2002

1999
Toward hardware building blocks for software-only real-time video processing: the MOVIE approach.
IEEE Trans. Circuits Syst. Video Techn., 1999

A flexible code generation framework for the design of application specific programmable processors.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1997
Architectural Study of a Block-Recursive Motion Estimation Algorithm.
Real-Time Imaging, 1997

1995
Efficient Parallel Nonlinear Multigrid Algorithms for Low-Level Vision Applications.
J. Parallel Distrib. Comput., 1995

MOVIE: A Building Block for the Design of Real Time Simulator of Moving Pictures Compression Algorithms.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994
From Equations to Hardware. Towards the Systematic Mapping of Algorithms onto Parallel Architectures.
IJPRAI, 1994

Efficient parallel multigrid relaxation algorithms for Markov random field-based low-level vision applications.
Proceedings of the Conference on Computer Vision and Pattern Recognition, 1994

1992
From Equations to Hardware: Towards Systematic Mapping of Algorithms onto Parallel Architectures.
Proceedings of the Parallel Image Analysis, Second International Conference, 1992

1990
Loop optimization for horizontal microcoded machines.
Proceedings of the 4th international conference on Supercomputing, 1990

1989
Overview of a high-performance programmable pipeline structure.
Proceedings of the 3rd international conference on Supercomputing, 1989

1986
Systolic architectures for connected speech recognition.
IEEE Trans. Acoustics, Speech, and Signal Processing, 1986


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