Omar Hammami

According to our database1, Omar Hammami authored at least 70 papers between 1989 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Defense program quality-cost-delay optimization: architecture framework, a bridge between program management and system engineering.
Syst. Eng., March, 2024

2023
Multi-objective Optimisation of RISC-V CV32A6 for ML application.
Proceedings of the 2023 IEEE International Conference on Design, 2023

A System Approach to Detect Medical Errors in Operational Data in Hospitals.
Proceedings of the 20th ACS/IEEE International Conference on Computer Systems and Applications, 2023

2022
Coupling Architecture Framework and Operation Research: the Case of NAF with Cost and Delay Driven Multi-Criteria Scheduling.
Proceedings of the 17th Annual System of Systems Engineering Conference, 2022

HPC Exploration for Mobile Robotics Under Energy Constraints.
Proceedings of the 31st IEEE International Symposium on Industrial Electronics, 2022

2020
Factors contributing to CT scan usability.
Proceedings of the IEEE International Conference on Computational Intelligence and Virtual Environments for Measurement Systems and Applications, 2020

2019
Evaluation of Invisible Physical and Mental Exertion from CT Scan Operation in Saudi Arabian Hospitals.
Proceedings of the 6th International Conference on Control, 2019

Effect of Invisible Exertions on Computed Tomography Radiologists in Saudi Hospitals.
Proceedings of the 16th IEEE/ACS International Conference on Computer Systems and Applications, 2019

2018
Evaluation of CT Scan Usability for Saudi Arabian Users.
Proceedings of the 2018 International Conference on Computer, 2018

User Experience of CT Scan: A Reflection of Usability and Exertions.
Proceedings of the 15th IEEE/ACS International Conference on Computer Systems and Applications, 2018

2016
Capella based system engineering modelling and multi-objective optimization of avionics systems.
Proceedings of the IEEE International Symposium on Systems Engineering, 2016

Multi-objective optimization of automotive electrical/energy storage system.
Proceedings of the IEEE International Conference on Industrial Technology, 2016

System Engineering Education for Confirmed Engineers: The FAIS case Study- A 6 years Feedback.
Proceedings of the Complex Systems Design & Management, 2016

High-level synthesis for FPGA design based-SLAM application.
Proceedings of the 13th IEEE/ACS International Conference of Computer Systems and Applications, 2016

2015
Architecture frameworks, multiobjective optimization and multiphysics simulation: Challenges and opportunities.
Proceedings of the Annual IEEE Systems Conference, 2015

THEFOSE - Theoretical Foundations of System Engineering: A first feedback.
Proceedings of the IEEE International Symposium on Systems Engineering, 2015

Multiobjective optimization of collaborative process for modeling and simulation - <Q, R, T>.
Proceedings of the IEEE International Symposium on Systems Engineering, 2015

2014
Rationalizing approaches to multi-objective optimization in systems architecture design.
Proceedings of the IEEE International Systems Conference, 2014

SYNSYS-ME: Seamless System Engineering to mechanical flow through multiobjective optimization and requirements analysis.
Proceedings of the IEEE International Systems Conference, 2014

Complex systems approximate matching approach for large graphs classification optimized by NSGA-II.
Proceedings of the 6th International Conference of Soft Computing and Pattern Recognition, 2014

2013
MHYNESYS II: Multi-stage hybrid Network on chip synthesis for Next Generation 3D IC Manycore.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

NOC based MPSOC directory based cache coherency with OCP-IP protocol.
Proceedings of the 8th International Design and Test Symposium, 2013

NOCBENCH: NOC synthesis benchmarks.
Proceedings of the 8th International Design and Test Symposium, 2013

NOC synthesis vs ITRS predictions: The challenges of linear programming based synthesis.
Proceedings of the 8th International Design and Test Symposium, 2013

Impact of 3D IC on NoC Topologies: A Wire Delay Consideration.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
NOCEVE: Network on chip emulation and verification environment.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Multi-objective topology synthesis and FPGA prototyping framework of application specific network-on-chip.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

3D multiprocessor with 3D NoC architecture based on Tezzaron technology.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Design of 3D-IC for butterfly NOC based 64 PE-multicore: Analysis and design space exploration.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Design and implementation of MPSoC single chip with butterfly network.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

SDR waveform components implementation on single FPGA multiprocessor platform.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Standard recognising self organizing map based cognitive radio transceiver.
Proceedings of the 5th International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2010

2009
An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography.
Int. J. Reconfigurable Comput., 2009

Performance measurements of synchronization mechanisms on 16PE NOC based multi-core with dedicated synchronization and data NOC.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Optimized joint NARX ANN - embedded processor design methodology.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008
A hybrid approach for training recurrent neural networks: application to multi-step-ahead prediction of noisy and large data sets.
Neural Comput. Appl., 2008

Automatic object and image alignment using Fourier Descriptors.
Image Vis. Comput., 2008

A Case Study: Quantitative Evaluation of C-Based High-Level Synthesis Systems.
EURASIP J. Embed. Syst., 2008

A quantitative evaluation of C-based synthesis on heterogeneous embedded systems design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

C-based hardware-accelerator coprocessing for SOC an quantitative area-performance evaluation.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Linear programming based design of reconfigurable network on chip on eFPGA.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
System-Platforms-Based SystemC TLM Design of Image Processing Chains for Embedded Applications.
EURASIP J. Embed. Syst., 2007

Graduate Education to Fight System Level Design Productivity Gap in SOC Design.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

2006
Application-specific SIMD synthesis for reconfigurable architectures.
Microprocess. Microsystems, 2006

MOCDEX: Multiprocessor on Chip Multiobjective Design Space Exploration with Direct Execution.
EURASIP J. Embed. Syst., 2006

NoC Monitoring Hardware Support for Fast NoC Design Space Exploration and Potential NoC Partial Dynamic Reconfiguration.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

NOCDEX: Network on Chip Design Space Exploration Through Direct Execution and Options Selection Through Principal Component Analysis.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

System-Level Design Methodology with Direct Execution For Multiprocessors on SoPC.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Multiprocessor on chip: beating the simulation wall through multiobjective design space exploration with direct execution.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

JPEG-2000 Workload Prediction for Adaptive System on Chip Entropy Coders Architecture.
Proceedings of the International Joint Conference on Neural Networks, 2006

Neural Network Based Memory Access Prediction Support for SoC Dynamic Reconfiguration.
Proceedings of the International Joint Conference on Neural Networks, 2006

Customized SIMD unit synthesis for system on programmable chip: a foundation for HW/SW partitioning with vectorization.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Dynamically reconfigurable analog circuit design automation through multiobjective optimization and direct execution.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

A combined FPAA-FPGA platform for mixed-signals design space exploration.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004
Multiobjective Design of Embedded Processors on FPGA Platforms.
Proceedings of the 24th International Conference on Distributed Computing Systems Workshops (ICDCS 2004 Workshops), 2004

Exploring JPEG-2000 entropy coder implementations on xilinx virtex-II pro platforms.
Proceedings of the 2004 12th European Signal Processing Conference, 2004

Analysis and Hardware Design of a Scalable Dual JPEG-2000 Entropy Coder.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

1999
Neural Network Classifiers Execution on Superscalar Microprocessors.
Proceedings of the High Performance Computing, Second International Symposium, 1999

Message from the PERH Workshop Co-Chairs.
Proceedings of the 1999 International Conference on Parallel Processing Workshops, 1999

SOM on multi-FPGA ISA board-hardware aspects.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
Reconfigurable hardware devices evoluation: an important opportunity for full span computer architecture education.
Proceedings of the 1998 workshop on Computer architecture education, 1998

Performance Impacts of Superscalar Microarchitecture on SOM Execution.
Proceedings of the Proceedings 31st Annual Simulation Symposium (SS '98), 1998

1997
A pipelined speculative SIMD architecture for SOM ANN.
Proceedings of International Conference on Neural Networks (ICNN'97), 1997

1995
Real time aspects of cluster based caches.
Proceedings of the 2nd International Workshop on Real-Time Computing Systems and Applications, October 25, 1995

Towards self organizing cache memories using neural networks.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

Fighting space complexity of compile time cache management schemes.
Proceedings of the 33th Annual Southeast Regional Conference, 1995

1994
A Novel Cache Management Using the A<sup>*</sup> Algorithm.
Proceedings of the Seventh International Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems, 1994

1989
Multiprocessors with a serial multiport memory and a pseudo crossbar of serial links used s a processor-memeory switch.
SIGARCH Comput. Archit. News, 1989

Serial Multiport Memory Multiprocessors.
Proceedings of the PARLE '89: Parallel Architectures and Languages Europe, 1989


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