Shinji Nishimura

According to our database1, Shinji Nishimura authored at least 18 papers between 1991 and 2014.

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Bibliography

2014
A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion.
IEEE J. Solid State Circuits, 2014

2013
Compact and power-efficient 100-Gbps CMOS-based transceiver.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013

2012
A Novel 400-Gb/s (100-Gb/s×4) Physical-Layer Architecture Using Low-Power Technology.
IEICE Trans. Commun., 2012

A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link.
IEEE J. Solid State Circuits, 2011

10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
100GbE PHY and MAC layer implementations.
IEEE Commun. Mag., 2010

A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2008
Technologies to Save Power for Carrier Class Routers and Switches.
Proceedings of the 2008 International Symposium on Applications and the Internet, 2008

A 100 Gb/s and High-Reliable Physical-Layer Architecture for VSR and Backplane Ethernet.
Proceedings of IEEE International Conference on Communications, 2008

2007
A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications.
IEICE Trans. Electron., 2007

Basic Simulation Result of Inter System Handover for Cognitive Radio.
Proceedings of the Future Generation Communication and Networking, 2007

2006
100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet.
IEICE Trans. Commun., 2006

Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic.
IEICE Trans. Electron., 2006

2005
A 100-Gb-Ethernet subsystem for next-generation metro-area network.
Proceedings of IEEE International Conference on Communications, 2005

2001
RHiNET-3/SW: an 80-Gbit/s high-speed network switch for distributed parallel computing.
Proceedings of the Ninth Symposium on High Performance Interconnects, 2001

2000
RHiNET-2/SW a Hight-throughput, Compact Network-switch Using 8.8-Gbit/s Optical Interconnection.
New Gener. Comput., 2000

1991
Single board video codec for ISDN visual telephone.
Proceedings of the 1991 International Conference on Acoustics, 1991


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