Hiroki Yamashita
According to our database1,
Hiroki Yamashita
authored at least 31 papers
between 2004 and 2020.
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Bibliography
2020
Approaching Behavior Analysis for Improving a Mobile Communication Robot in a Nursing Home.
Proceedings of the HCI International 2020 - Late Breaking Papers: Universal Access and Inclusive Design, 2020
2018
A 50-Gb/s High-Sensitivity (-9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18-µm SiGe BiCMOS Technology.
IEEE J. Solid State Circuits, 2018
25-Gbps 3-mW/Gbps/ch VCSEL Driver Circuit in 65-nm CMOS for Multichannel Optical Transmitter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
2017
Low-light color image enhancement via iterative noise reduction using RGB/NIR sensor.
J. Electronic Imaging, 2017
RGB-NIR imaging with exposure bracketing for joint denoising and deblurring of low-light color images.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017
2016
A 50-Gb/s Optical Transmitter Based on a 25-Gb/s-Class DFB-LD and a 0.18-µm SiGe BiCMOS LD Driver.
IEICE Trans. Electron., 2016
A 50.6-Gb/s 7.8-mW/Gb/s -7.4-dBm sensitivity optical receiver based on 0.18-µm SiGe BiCMOS technology.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016
2015
Enhancing Color Images of Extremely Low Light Scenes Based on RGB/NIR Images Acquisition With Different Exposure Times.
IEEE Trans. Image Process., 2015
Proceedings of the 2015 Visual Communications and Image Processing, 2015
A 50-Gb/s NRZ-modulated optical transmitter based on a DFB-LD and a 0.18-µm SiGe BiCMOS LD driver.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
An electrical and optical concurrent design methodology for enlarging jitter margin of 25.8-Gb/s optical interconnects.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion.
IEEE J. Solid State Circuits, 2014
A 25-to-28 Gb/s High-Sensitivity (-9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects.
IEEE J. Solid State Circuits, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
A 25-Gb/s × 4-Ch, 8 × 8 mm<sup>2</sup>, 2.8-mm thick compact optical transceiver module for on-board optical interconnect.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
A 4× 25-to-28Gb/s 4.9mW/Gb/s -9.7dBm high-sensitivity optical receiver based on 65nm CMOS for board-to-board interconnects.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
2011
IEEE J. Solid State Circuits, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
IEEE J. Solid State Circuits, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS.
IEEE J. Solid State Circuits, 2009
10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1<sup>st</sup>-order ΔΣ modulator.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2006
2005
A 1.2Gb/s write driver with pre-emphasis overshoot control optimized for high density HDD applications.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking.
IEEE J. Solid State Circuits, 2004