Hidehiro Toyoda

According to our database, Hidehiro Toyoda authored at least 14 papers between 2005 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Simultaneous multi-ONU wavelength switching method for coexistence of different λ-tuning times in WDM/TDM-PON.

Jun Sugawa, Koji Wakayama, Hidehiro Toyoda

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

Adaptive FEC control in downstream collaborating with traffic control in OLT for WDM/TDM-PON.

Jun Sugawa, Koji Wakayama, Hidehiro Toyoda

Proceedings of the European Conference on Optical Communication, 2015

2014

A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion.

Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Yong Lee, Shinji Tsuji, Shinji Nishimura

IEEE J. Solid State Circuits, 2014

Wavelength switching method combined with downstream queue monitoring per ONU for λ-tunable WDM/TDM-PON.

Jun Sugawa, Toshiyuki Odaka, Hidehiro Toyoda

Proceedings of the European Conference on Optical Communication, 2014

2012

A Novel 400-Gb/s (100-Gb/s×4) Physical-Layer Architecture Using Low-Power Technology.

Masashi Kono, Akihiro Kambe, Hidehiro Toyoda, Shinji Nishimura

IEICE Trans. Commun., 2012

A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS.

Takashi Takemoto, Hiroki Yamashita, Takehito Kamimura, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Kenji Kogo, Yong Lee, Shinji Tsuji, Shinji Nishimura

Proceedings of the Symposium on VLSI Circuits, 2012

2011

A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link.

Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura

IEEE J. Solid State Circuits, 2011

10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link.

Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 400-Gb/s and Low-Power Physical-Layer Architecture for Next-Generation Ethernet.

Masashi Kono, Akihiro Kambe, Hidehiro Toyoda

Proceedings of IEEE International Conference on Communications, 2011

2010

100GbE PHY and MAC layer implementations.

Hidehiro Toyoda, Goichi Ono, Shinji Nishimura

IEEE Commun. Mag., 2010

2008

A 100 Gb/s and High-Reliable Physical-Layer Architecture for VSR and Backplane Ethernet.

Hidehiro Toyoda, Michitaka Okuno, Shinji Nishimura, Matsuaki Terada

Proceedings of IEEE International Conference on Communications, 2008

2007

A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications.

Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Matsuaki Terada

IEICE Trans. Electron., 2007

2006

100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet.

Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Kouji Fukuda, Kouji Nakahara, Hiroaki Nishi

IEICE Trans. Commun., 2006

2005

A 100-Gb-Ethernet subsystem for next-generation metro-area network.

Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Ryouji Yamaoka, Hiroaki Nishi

Proceedings of IEEE International Conference on Communications, 2005