Furkan Ercan

Orcid: 0000-0003-0599-1766

According to our database1, Furkan Ercan authored at least 32 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Modeling and Simulation for the Operative Service Delivery Planning in the Context of Product-Service Systems.
Proceedings of the Winter Simulation Conference, 2023

Demo: Universal Soft-Detection Decoder with Ultra-Low Energy Consumption Using ORBGRAND.
Proceedings of the 24th IEEE International Symposium on a World of Wireless, 2023

A Sub-0.8pJ/b 16.3Gbps/mm<sup>2</sup> Universal Soft-Detection Decoder Using ORBGRAND in 40nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

GRAND-EDGE: A Universal, Jamming-Resilient Algorithm with Error-and-Erasure Decoding.
Proceedings of the IEEE International Conference on Communications, 2023

Noise Recycling using GRAND for Improving the Decoding Performance.
Proceedings of the 15th International Conference on COMmunication Systems & NETworkS, 2023

2022
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Interleaved Noise Recycling using GRAND.
Proceedings of the IEEE International Conference on Communications, 2022

A General Security Approach for Soft-information Decoding against Smart Bursty Jammers.
Proceedings of the IEEE Globecom 2022 Workshops, 2022

2021
Neural Successive Cancellation Flip Decoding of Polar Codes.
J. Signal Process. Syst., 2021

Design of an Artificial Neural Network Circuit for detecting Atrial Fibrillation in ECG Signals.
Proceedings of the 2021 IEEE Sensors, Sydney, Australia, October 31 - Nov. 3, 2021, 2021

Fast SC-Flip Decoding of Polar Codes with Reinforcement Learning.
Proceedings of the ICC 2021, 2021

High-Throughput VLSI Architecture for Soft-Decision Decoding with ORBGRAND.
Proceedings of the IEEE International Conference on Acoustics, 2021

2020
Practical Dynamic SC-Flip Polar Decoders: Algorithm and Implementation.
IEEE Trans. Signal Process., 2020

Energy-Efficient Hardware Architectures for Fast Polar Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

High-Throughput VLSI Architecture for GRAND.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

Fast Thresholded SC-Flip Decoding of Polar Codes.
Proceedings of the 2020 IEEE International Conference on Communications, 2020

Simplified Dynamic SC-Flip Polar Decoding.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

2019
Operation Merging for Hardware Implementations of Fast Polar Decoders.
J. Signal Process. Syst., 2019

Improved Bit-Flipping Algorithm for Successive Cancellation Decoding of Polar Codes.
IEEE Trans. Commun., 2019

Design and Implementation of a Polar Codes Blind Detection Scheme.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Neural Dynamic Successive Cancellation Flip Decoding of Polar Codes.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

A Novel Offset and 1/f Noise Compensated Single-Slope ADC with Reduced Hardware Effort.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

2018
Improved successive cancellation flip decoding of polar codes based on error distribution.
Proceedings of the 2018 IEEE Wireless Communications and Networking Conference Workshops, 2018

Partitioned Successive-Cancellation Flip Decoding of Polar Codes.
Proceedings of the 2018 IEEE International Conference on Communications, 2018

2017
Memory-Efficient Polar Decoders.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017

Reduced-memory high-throughput fast-SSC polar code decoder architecture.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

On error-correction performance and implementation of polar code list decoders for 5G.
Proceedings of the 55th Annual Allerton Conference on Communication, 2017

On the performance of polar codes for 5G eMBB control channel.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2015
Power-delay analysis of an ABACUS parallel integer multiplier VLSI implementation.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015

Comparative power-delay performance analysis of threshold logic technologies.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015

2013
Energy-delay performance of capacitive threshold logic (CTL) circuits for threshold detection.
Proceedings of the 4th Annual International Conference on Energy Aware Computing Systems and Applications, 2013

2012
An integrated approach to system-level CPU and memory energy efficiency on computing systems.
Proceedings of the International Conference on Energy Aware Computing, 2012


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