Arash Ardakani

Orcid: 0000-0003-3274-2394

According to our database1, Arash Ardakani authored at least 27 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
SlimFit: Memory-Efficient Fine-Tuning of Transformer-based Models Using Training Dynamics.
Proceedings of the 2024 Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies (Volume 1: Long Papers), 2024

2022
Standard Deviation-Based Quantization for Deep Neural Networks.
CoRR, 2022

Partially-Random Initialization: A Smoking Gun for Binarization Hypothesis of BERT.
Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2022, 2022

2021
Hardware-Aware Design for Edge Intelligence.
IEEE Open J. Circuits Syst., 2021

Training Binarized Neural Networks Using Ternary Multipliers.
IEEE Des. Test, 2021

Fault-Tolerance of Binarized and Stochastic Computing-based Neural Networks.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

2020
Fast and Efficient Convolutional Accelerator for Edge Computing.
IEEE Trans. Computers, 2020

Training Linear Finite-State Machines.
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020

A Regression-Based Method to Synthesize Complex Arithmetic Computations on Stochastic Streams.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Design and Implementation of a Polar Codes Blind Detection Scheme.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

The Synthesis of XNOR Recurrent Neural Networks with Stochastic Logic.
Proceedings of the Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, 2019

Learning Recurrent Binary/Ternary Weights.
Proceedings of the 7th International Conference on Learning Representations, 2019

Learning to Skip Ineffectual Recurrent Computations in LSTMs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
An Architecture to Accelerate Convolution in Deep Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Multi-Mode Accelerator for Pruned Deep Neural Networks.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

A Convolutional Accelerator for Neural Networks With Binary Weights.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Multi-Mode Inference Engine for Convolutional Neural Networks.
CoRR, 2017

A low-complexity fully scalable interleaver/address generator based on a novel property of QPP interleavers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Sparsely-Connected Neural Networks: Towards Efficient VLSI Implementation of Deep Neural Networks.
Proceedings of the 5th International Conference on Learning Representations, 2017

Activation pruning of deep convolutional neural networks.
Proceedings of the 2017 IEEE Global Conference on Signal and Information Processing, 2017

2016
Stochastic Computing Can Improve Upon Digital Spiking Neural Networks.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

VLSI implementation of deep neural networks using integral stochastic computing.
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

Hardware implementation of FIR/IIR digital filters using integral stochastic computation.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

2015
A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

An efficient max-log MAP algorithm for VLSI implementation of turbo decoders.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2013
An efficient VLSI architecture of QPP interleaver/deinterleaver for LTE turbo coding.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013


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