Georg T. Becker

Orcid: 0000-0002-1200-1508

According to our database1, Georg T. Becker authored at least 26 papers between 2010 and 2022.

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Bibliography

2022
Automated benchmark network diversification for realistic attack simulation with application to moving target defense.
Int. J. Inf. Sec., 2022

2021
Combining Optimization Objectives: New Modeling Attacks on Strong PUFs.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

2020
dPHI: An improved high-speed network-layer anonymity protocol.
Proc. Priv. Enhancing Technol., 2020

Combining Optimization Objectives: New Machine-Learning Attacks on Strong PUFs.
IACR Cryptol. ePrint Arch., 2020

A critical view on moving target defense and its analogies.
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020

2019
Robust Fuzzy Extractors and Helper Data Manipulation Attacks Revisited: Theory versus Practice.
IEEE Trans. Dependable Secur. Comput., 2019

Breaking the Lightweight Secure PUF: Understanding the Relation of Input Transformations and Machine Learning Resistance.
IACR Cryptol. ePrint Arch., 2019

2018
Bitstream Fault Injections (BiFI)-Automated Fault Attacks Against SRAM-Based FPGAs.
IEEE Trans. Computers, 2018

Attack Simulation for a Realistic Evaluation and Comparison of Network Security Techniques.
Proceedings of the Secure IT Systems - 23rd Nordic Conference, NordSec 2018, Oslo, Norway, 2018

2017
Robust Fuzzy Extractors and Helper Data Manipulation Attacks Revisited: Theory vs Practice.
IACR Cryptol. ePrint Arch., 2017

A fair and comprehensive large-scale analysis of oscillation-based PUFs for FPGAs.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
A Design Methodology for Stealthy Parametric Trojans and Its Application to Bug Attacks.
IACR Cryptol. ePrint Arch., 2016

On the problems of realizing reliable and efficient ring oscillator PUFs on FPGAs.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

2015
On the Pitfalls of Using Arbiter-PUFs as Building Blocks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

On the Scaling of Machine Learning Attacks on PUFs with Application to Noise Bifurcation.
Proceedings of the Radio Frequency Identification. Security and Privacy Issues, 2015

Development of a Layout-Level Hardware Obfuscation Tool.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Security analysis of index-based syndrome coding for PUF-based key generation.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

The Gap Between Promise and Reality: On the Insecurity of XOR Arbiter PUFs.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2015, 2015

2014
Stealthy dopant-level hardware Trojans: extended version.
J. Cryptogr. Eng., 2014

Active and Passive Side-Channel Attacks on Delay Based PUF Designs.
IACR Cryptol. ePrint Arch., 2014

2013
Stealthy Dopant-Level Hardware Trojans.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2013, 2013

2012
Detecting Software Theft in Embedded Systems: A Side-Channel Approach.
IEEE Trans. Inf. Forensics Secur., 2012

Side channels as building blocks.
J. Cryptogr. Eng., 2012

2011
Implementing hardware Trojans: Experiences from a hardware Trojan challenge.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010
Side-channel based Watermarks for Integrated Circuits.
Proceedings of the HOST 2010, 2010

Secure Location Verification - A Security Analysis of GPS Signal Authentication.
Proceedings of the Data and Applications Security and Privacy XXIV, 2010


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