Vikram B. Suresh

According to our database1, Vikram B. Suresh authored at least 16 papers between 2010 and 2019.

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Bibliography

2019
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS.
J. Solid-State Circuits, 2019

2016
Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

2015
Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing.
IEEE Trans. on Circuits and Systems, 2015

2014
REFLEX: Reconfigurable logic for entropy extraction.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Post-Silicon Validation and Calibration of Hardware Security Primitives.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Variation Aware Design of Post-Silicon Tunable Clock Buffer.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Fine grained wearout sensing using metastability resolution time.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013
On analyzing and mitigating SRAM BER due to random thermal noise.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Managing test coverage uncertainty due to thermal noise in nano-CMOS: A case-study on an SRAM array.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

On-chip lightweight implementation of reduced NIST randomness test suite.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

2012
On lithography aware metal-fill insertion.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011
Lithography aware critical area estimation and yield analysis.
Proceedings of the 2011 IEEE International Test Conference, 2011

On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Implementing hardware Trojans: Experiences from a hardware Trojan challenge.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010
Entropy Extraction in Metastability-based TRNG.
Proceedings of the HOST 2010, 2010


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