# Vikram B. Suresh

According to our database

Collaborative distances:

^{1}, Vikram B. Suresh authored at least 50 papers between 2010 and 2020.Collaborative distances:

## Timeline

#### Legend:

Book In proceedings Article PhD thesis Other## Links

#### On csauthors.net:

## Bibliography

2020

A 4900- $\mu$ m<sup>2</sup> 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition.

IEEE J. Solid State Circuits, 2020

A 0.26% BER, 10<sup>28</sup> Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection.

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS.

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures.

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS.

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range.

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

INVITED: A 0.26% BER, Machine-Learning Resistant 10<sup>28</sup> Challenge-Response PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection.

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS.

IEEE J. Solid State Circuits, 2019

A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking.

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array.

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 4900×m<sup>2</sup> 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition.

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS.

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS.

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS.

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS.

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018

220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(2<sup>4</sup>)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS.

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms.

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS.

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS.

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms.

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS.

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS.

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017

A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS.

IEEE J. Solid State Circuits, 2017

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies.

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS.

IEEE J. Solid State Circuits, 2016

250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS.

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS.

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS.

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing.

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS.

IEEE J. Solid State Circuits, 2015

μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS.

Proceedings of the ESSCIRC Conference 2015, 2015

2014

340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(2<sup>4</sup>)<sup>2</sup> polynomials in 22nm tri-gate CMOS.

Proceedings of the Symposium on VLSI Circuits, 2014

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Managing test coverage uncertainty due to thermal noise in nano-CMOS: A case-study on an SRAM array.

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

2012

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration.

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011

Proceedings of the 2011 IEEE International Test Conference, 2011

On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements.

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010

Proceedings of the HOST 2010, 2010