Marcello Ganzerli

According to our database1, Marcello Ganzerli authored at least 8 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
32.6 A 76-to-81GHz Direct-Digital 7b 14GS/s Double-Balanced I/Q Mixing-DAC Radar-Waveform Synthesizer.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022
A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving 12nV/sqrt(Hz) 1/f noise at 153kHz and -104.7dBc THD in 30MHz BW.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021
A Novel 2-Dimensional Correction Method for mm-Wave Cartesian I/Q Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Time Interleaved ADC Mismatch Error Correction Technique in I/Q Digital Beamforming Receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2013
A 6-bit 6-GS/s 95mW background calibrated flash ADC with integrating preamplifiers and half-rate comparators in 32nm LP CMOS.
Proceedings of the ESSCIRC 2013, 2013

2011
An inductor-less 13.5-Gbps 8-mW analog equalizer for multi-channel multi-frequency operation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A MEMS reconfigurable quad-band Class-E Power Amplifier for GSM standard.
Proceedings of the Design, Automation and Test in Europe, 2009


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