Ghaith Bany Hamad
Orcid: 0000-0002-4354-2710
According to our database1,
Ghaith Bany Hamad
authored at least 32 papers
between 2011 and 2022.
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Bibliography
2022
Layout-based Vulnerability Analysis of LEON3 Processor to Single Event Multiple Transients using Satisfiability Modulo Theories.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
2021
Towards Safe and Robust Closed-Loop Artificial Pancreas Using Improved PID-Based Control Strategies.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
IEEE Trans. Ind. Informatics, 2020
Towards Safe and Robust Closed-Loop Artificial Pancreas Using Adaptive Weighted PID Control Strategy.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
System-Level Analysis of Closed-Loop Anesthesia Control Under Temporal Sensor Faults via UPPAAL-SMC.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
Detecting Malicious Ethereum Entities via Application of Machine Learning Classification.
Proceedings of the 2nd Conference on Blockchain Research & Applications for Innovative Networks and Services, 2020
2019
Towards an Accurate Probabilistic Modeling and Statistical Analysis of Temporal Faults via Temporal Dynamic Fault-Trees (TDFTs).
IEEE Access, 2019
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Reliability Analysis of TSN Networks Under SEU Induced Soft Error Using Model Checking.
Proceedings of the IEEE Latin American Test Symposium, 2019
Probabilistic High-Level Estimation of Vulnerability and Fault Mitigation of Critical Systems Using Fault-Mitigation Trees (FMTs).
Proceedings of the IEEE Latin American Test Symposium, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the Advances and Trends in Artificial Intelligence. From Theory to Practice, 2019
2018
New Insights Into Soft-Faults Induced Cardiac Pacemakers Malfunctions Analyzed at System-Level via Model Checking.
IEEE Access, 2018
Fault-Resilient Topology Planning and Traffic Configuration for IEEE 802.1Qbv TSN Networks.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the Recent Trends and Future Technology in Applied Intelligence, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits.
J. Electron. Test., 2017
Analysis of SEU propagation in sequential circuits at RTL using Satisfiability Modulo Theories.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Comprehensive analysis of sequential circuits vulnerability to transient faults using SMT.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo Theories.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
2016
Towards formal abstraction, modeling, and analysis of Single Event Transients at RTL.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Investigating the efficiency and accuracy of a data type reduction technique for soft error analysis.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Efficient and accurate analysis of single event transients propagation using SMT-based techniques.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Comprehensive non-functional analysis of combinational circuits vulnerability to single event transients.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016
Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checking.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016
2015
Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits.
Microelectron. Reliab., 2015
Efficient multilevel formal analysis and estimation of design vulnerability to Single Event Transients.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
2014
Modeling, analyzing, and abstracting single event transient propagation at gate level.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Abstracting Single Event Transient characteristics variations due to input patterns and fan-out.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
SEGP-Finder: Tool for identification of Soft Error Glitch-Propagating paths at gate level.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011