Takayuki Kawahara
Orcid: 0000-0002-7130-3397
According to our database1,
Takayuki Kawahara
authored at least 59 papers
between 1995 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2007, "For contributions to low-voltage low-power random access memory circuits".
Timeline
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On csauthors.net:
Bibliography
2024
Scalable Fully-Coupled Annealing Processing System Implementing 4096 Spins Using 22nm CMOS LSI.
IEEE Access, 2024
2023
Experimental Investigation of the Generalization Performance of Neural Network in Defect Localization System for Steel Pipe Health Monitoring.
Proceedings of the IEEE Region 10 Conference, 2023
Proceedings of the IEEE Region 10 Conference, 2023
2022
Scalable fully coupled annealing processing system and multi-chip FPGA implementation.
Microprocess. Microsystems, November, 2022
Bi-directional read method to reduce SOT-specific read disturbance for highly reliable SOT-MRAM.
Proceedings of the IEEE International Memory Workshop, 2022
2021
Annealing Processing Architecture of 28-nm CMOS Chip for Ising Model With 512 Fully Connected Spins.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Proceedings of the IEEE International Conference on Computational Intelligence and Virtual Environments for Measurement Systems and Applications, 2021
2020
A novel Ising model processing achieving all interactions only by adjacent spins for a high-speed solver for versatile Ising machines.
Microprocess. Microsystems, 2020
Implementation of Multi Spin-Thread Architecture to Fully-Connected Annealing Processing AI Chips.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Improvement of Generalization Performance for Timber Health Monitoring using Machine Learning.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
Damage-Position Identification of Wooden-House Models for Structural Health Monitoring Using Machine Learning.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Machine Learning Classification Methods using Data of 3-axis Acceleration Sensors equipped with Wireless Communication Means for Locating Wooden House Structural Damage.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
Effectiveness of Synchronization and Cooperative Behavior of Multiple Robots based on Swarm AI.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
Live Demonstration of IoT and AI System for Recognition of States of Buildings subjected to Seismic Vibration Motion.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Wooden Framed House Structural Health Monitoring by System Identification and Damage Detection under Dynamic Motion with Artificial Intelligence Sensor using a Model of House including Braces.
Proceedings of the IEEE International Conference on Computational Intelligence and Virtual Environments for Measurement Systems and Applications, 2018
2017
A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design.
IEICE Trans. Electron., 2017
Robustness Evaluation of Restricted Boltzmann Machine against Memory and Logic Error.
IEICE Trans. Electron., 2017
Proceedings of the IEEE International Conference on Computational Intelligence and Virtual Environments for Measurement Systems and Applications, 2017
2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
2015
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015
An eight-channel FDM system using Mach-Zehnder filters with cosine roll-off band-limiting characteristics.
Proceedings of the 10th Asia-Pacific Symposium on Information and Telecommunication Technologies, 2015
Proceedings of the 29th IEEE International Conference on Advanced Information Networking and Applications Workshops, 2015
2014
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
On-chip base sequencing using a two-stage reaction-control scheme: 3.6-times-faster and 1/100-reduced-data-volume ISFET-based DNA sequencer.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013
2012
Microelectron. Reliab., 2012
Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device.
IEICE Trans. Electron., 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Des. Test Comput., 2011
2010
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme.
IEEE J. Solid State Circuits, 2010
2008
2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read.
IEEE J. Solid State Circuits, 2008
A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis.
Proceedings of the ESSCIRC 2008, 2008
2007
Long-Retention-Time, High-Speed DRAM Array with 12-<i>F</i><sup>2</sup> Twin Cell for Sub 1-V Operation.
IEICE Trans. Electron., 2007
2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors.
IEEE J. Solid State Circuits, 2006
90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique.
IEEE J. Solid State Circuits, 2006
Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM.
IEEE J. Solid State Circuits, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories.
IEEE J. Solid State Circuits, 2005
A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router.
IEEE J. Solid State Circuits, 2005
An LSI system with locked in temperature insensitive state achieved by using body bias technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup.
Proceedings of IEEE International Conference on Communications, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect.
IEEE J. Solid State Circuits, 2004
Proceedings of the Integrated Circuit and System Design, 2004
Temperature referenced supply voltage and forward-body-bias control (TSFC) architecture for minimum power consumption [ubiquitous computing processors].
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experiment.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
1998
IEEE J. Solid State Circuits, 1998
IEEE J. Solid State Circuits, 1998
1996
Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories.
IEEE J. Solid State Circuits, 1996
1995
IEEE J. Solid State Circuits, December, 1995