Greg Aldrich

According to our database, Greg Aldrich authored at least 5 papers between 2002 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

A RTL Testability Analyzer Based on Logical Virtual Prototyping.

Yu Huang, Nilanjan Mukherjee, Wu-Tung Cheng, Greg Aldrich

Proceedings of the 16th Asian Test Symposium, 2007

2006

Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis.

Nandu Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-Tung Cheng, Alex Babin, Kun-Han Tsai, Nagesh Tamarapalli, Greg Aldrich

Proceedings of the 2006 IEEE International Test Conference, 2006

Mentor Graphics DFT to Navigate Nanometer Test Challenges.

Greg Aldrich, Ron Press, Takeo Kobayashi, Tatsuo Sakajiri

Proceedings of the 15th Asian Test Symposium, 2006

2004

100 DPPM in Nanometer Technology - Is it achievable?

Greg Aldrich

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2002

Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.

Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002