Nagesh Tamarapalli

According to our database1, Nagesh Tamarapalli authored at least 22 papers between 1996 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2015
Tutorial T5: High Performance Low Power Designs - Challenges and Best practices in Design, Verification and Test.
Proceedings of the 28th International Conference on VLSI Design, 2015

2014
Application of Test-View Modeling to Hierarchical ATPG.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013
Tutorial T10: Post - Silicon Validation, Debug and Diagnosis.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2012
Tutorial T3: DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield.
Proceedings of the 25th International Conference on VLSI Design, 2012

2008
DFM / DFT / SiliconDebug / Diagnosis.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2006
DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis.
Proceedings of the 2006 IEEE International Test Conference, 2006

A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis.
Proceedings of the 2006 IEEE International Test Conference, 2006

Diagnosis with Limited Failure Information.
Proceedings of the 2006 IEEE International Test Conference, 2006

The Next Step in Volume Scan Diagnosis: Standard Fail Data Format.
Proceedings of the 15th Asian Test Symposium, 2006

2005
Achieving higher yield through diagnosis.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Compression mode diagnosis enables high volume monitoring diagnosis flow.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
Compactor Independent Direct Diagnosis.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Embedded Deterministic Test for Low-Cost Manufacturing.
IEEE Des. Test Comput., 2003

High-Frequency, At-Speed Scan Testing.
IEEE Des. Test Comput., 2003

Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Impact of Multiple-Detect Test Patterns on Product Quality.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Embedded Deterministic Test for Low-Cost Manufacturing Test.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2000
Automated synthesis of phase shifters for built-in self-testapplications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1999
Logic BIST for large industrial designs: real issues and case studies.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
Automated synthesis of large phase shifters for built-in self-test.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1996
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996


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