Guido Albasini

Orcid: 0000-0003-0457-5808

According to our database1, Guido Albasini authored at least 10 papers between 2003 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
A 112 Gb/s PAM-4 RX Front-End With Unclocked Decision Feedback Equalizer.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2019
A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS.
IEEE J. Solid State Circuits, 2019

2018
A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
A 2-11 GHz 7-Bit High-Linearity Phase Rotator Based on Wideband Injection-Locking Multi-Phase Generation for High-Speed Serial Links in 28-nm CMOS FDSOI.
IEEE J. Solid State Circuits, 2017

2016
A 0.2-11.7GHz, high accuracy injection-locking multi-phase generation with mixed analog/digital calibration loops in 28nm FDSOI CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2007
A Magnetically Tuned Quadrature Oscillator.
IEEE J. Solid State Circuits, 2007

A 3.2-to-7.3GHz Quadrature Oscillator with Magnetic Tuning.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2004
A 700-kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications.
IEEE J. Solid State Circuits, 2004

2003
An UMTS ΣΔ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniques.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003


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