Massimo Pozzoni
According to our database1,
Massimo Pozzoni
authored at least 13 papers
between 2004 and 2019.
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Bibliography
2019
A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS.
IEEE J. Solid State Circuits, 2019
2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2013
A 6-bit 6-GS/s 95mW background calibrated flash ADC with integrating preamplifiers and half-rate comparators in 32nm LP CMOS.
Proceedings of the ESSCIRC 2013, 2013
2011
IEEE J. Solid State Circuits, 2011
2010
IEEE J. Solid State Circuits, 2010
A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A 13.1% tuning range 115GHz frequency generator based on an injection-locked frequency doubler in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
A 10Gb/s receiver with linear backplane equalization and mixer-based self-aligned CDR.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2005
A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability.
IEEE Trans. Very Large Scale Integr. Syst., 2005
2004
A high-speed low-voltage phase detector for clock recovery from NRZ data.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004