Ivan Bietti

According to our database, Ivan Bietti authored at least 10 papers between 1997 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET.

Matteo Pisati, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta, Demetrio Pellicone, Giorgio Spelgatti, Massimo Cutrupi, Andrea Rossini, Roberto G. Massolini, Giovanni Cesura, Ivan Bietti

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2006

Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End.

Antonio Liscidini, Cesare Ghezzi, Emanuele Depaoli, Guido Albasini, Ivan Bietti, Rinaldo Castello

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

A 72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner.

Mario Valla, Giampiero Montagna, Rinaldo Castello, Riccardo Tonietto, Ivan Bietti

IEEE J. Solid State Circuits, 2005

2004

A 700-kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications.

Enrico Temporiti, Guido Albasini, Ivan Bietti, Rinaldo Castello, Matteo Colombo

IEEE J. Solid State Circuits, 2004

2003

A 35-mW 3.6-mm2 fully integrated 0.18-μm CMOS GPS radio.

Giampiero Montagna, Giuseppe Gramegna, Ivan Bietti, Massimo Franciotta, Andrea Baschirotto, Placido De Vita, Roberto Pelleriti, Mario Paparo, Rinaldo Castello

IEEE J. Solid State Circuits, 2003

A 15 mW, 70 kHz 1/f corner direct conversion CMOS receiver.

Enrico Sacchi, Ivan Bietti, Simone Erbat, Luns Tee, Paolo Vilmercati, Rinaldo Castello

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

An UMTS ΣΔ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniques.

Ivan Bietti, Enrico Temporiti, Guido Albasini, Rinaldo Castello

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2000

A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi.

Giacomino Bollati, Angelo Dati, Giorgio Betti, Ivan Bietti, Francesco Brianti, Melchiorre Bruccoleri, M. Coltella, P. Demartini, Marco Demicheli, Paolo Gadducci, Stefano Marchese, Daniele Ottini, Valerio Pisati, Francesco Rezzi, A. Rossi, P. Savo, C. Tonci, Rinaldo Castello

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1997

A 70-mW seventh-order filter with 7-50 MHz cutoff frequency and programmable boost and group delay equalization.

Francesco Rezzi, Ivan Bietti, Marco Cazzaniga, Rinaldo Castello

IEEE J. Solid State Circuits, 1997

A 200-MSample/s trellis-coded PRML read/write channel with analog adaptive equalizer and digital servo.

Roberto Alini, Giorgio Betti, Ivan Bietti, Giacomino Bollati, Francesco Brianti, Angelo Dati, Marco Demicheli, Paolo Gadducci, Stefano Marchese, Emanuele Marconetti, Valerio Pisati, Maurizio Zuffada, Rinaldo Castello, Fereidoon Heydari, Peter Gillen, Gerry Maguire, Marcus Marrow, Stephen McDonagh, Fergus O'Brien, Jerry O'Brien, Niall O'hEarcain, Deirdre Reddy, Lisa Fredrickson, Dennis Stone, LeRoy Volz

IEEE J. Solid State Circuits, 1997