Hai Zhou

According to our database1, Hai Zhou authored at least 183 papers between 1996 and 2019.

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Bibliography

2019
R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction.
IEEE Trans. VLSI Syst., 2019

Vulnerability and Remedy of Stripped Function Logic Locking.
IACR Cryptology ePrint Archive, 2019

Resolving the Trilemma in Logic Encryption.
IACR Cryptology ePrint Archive, 2019

BeSAT: Behavioral SAT-based Attack on Cyclic Logic Encryption.
IACR Cryptology ePrint Archive, 2019

SigAttack: New High-level SAT-based Attack on Logic Encryptions.
IACR Cryptology ePrint Archive, 2019

Rescuing Logic Encryption in Post-SAT Era by Locking & Obfuscation.
IACR Cryptology ePrint Archive, 2019

CycSAT-Unresolvable Cyclic Logic Encryption Using Unreachable States.
IACR Cryptology ePrint Archive, 2019

CellScope: Automatically Specifying and Verifying Cellular Network Protocols.
Proceedings of the ACM SIGCOMM 2019 Conference Posters and Demos, 2019

An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization.
IEEE Trans. VLSI Syst., 2018

Design and Synthesis of Self-Healing Memristive Circuits for Timing Resilient Processor Design.
IEEE Trans. VLSI Syst., 2018

An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis.
ACM Trans. Design Autom. Electr. Syst., 2018

Spraying trajectory Planning for outer-Horn surface with two patches based on continuous varied Dip-angle.
Int. J. Robotics Autom., 2018

A Capacitive Coupled Patch Antenna Array With High Gain and Wide Coverage for 5G Smartphone Applications.
IEEE Access, 2018

Chapter Three - Multiobjectivism in Dark Silicon Age.
Advances in Computers, 2018

Contact Force/Torque Prediction and Analysis Model for Large Length-diameter Ratio Peg-in-hole Assembly.
Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2018

R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

2017
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation.
ACM Trans. Design Autom. Electr. Syst., 2017

CycSAT: SAT-Based Attack on Cyclic Logic Encryptions.
IACR Cryptology ePrint Archive, 2017

A Humble Theory and Application for Logic Encryption.
IACR Cryptology ePrint Archive, 2017

Double DIP: Re-Evaluating Security of Logic Encryption Algorithms.
IACR Cryptology ePrint Archive, 2017

SAT-based Bit-flipping Attack on Logic Encryptions.
IACR Cryptology ePrint Archive, 2017

A Comparative Investigation of Approximate Attacks on Logic Encryptions.
IACR Cryptology ePrint Archive, 2017

Cyclic Locking and Memristor-based Obfuscation Against CycSAT and Inside Foundry Attacks.
IACR Cryptology ePrint Archive, 2017

Multi-objective Task Mapping Approach for Wireless NoC in Dark Silicon Age.
Proceedings of the 25th Euromicro International Conference on Parallel, 2017

Memristor-Based Clock Design and Optimization with In-Situ Tunability.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A Novel N-Retry Transactional Memory Model for Multi-Thread Programming.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Using Security Invariant To Verify Confidentiality in Hardware Design.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Network flow based cut redistribution and insertion for advanced 1D layout design.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

An efficient algorithm for stencil planning and optimization in E-beam lithography.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Rectilinear Steiner Tree.
Encyclopedia of Algorithms, 2016

Rectilinear Spanning Tree.
Encyclopedia of Algorithms, 2016

Circuit Retiming: An Incremental Approach.
Encyclopedia of Algorithms, 2016

Circuit Retiming.
Encyclopedia of Algorithms, 2016

Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

A Security Mechanism for Cluster-Based WSN against Selective Forwarding.
Sensors, 2016

Spray Technology Planning of spray Painting robot for Complex Free surface.
Int. J. Robotics Autom., 2016

Recent advances on application of deep learning for recovering object pose.
Proceedings of the 2016 IEEE International Conference on Robotics and Biomimetics, 2016

2015
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography.
ACM Trans. Design Autom. Electr. Syst., 2015

Multi-parameter clock skew scheduling.
Integr., 2015

Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Synthesis of resilient circuits from guarded atomic actions.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Optimal and Efficient Algorithms for Multidomain Clock Skew Scheduling.
IEEE Trans. VLSI Syst., 2014

Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers.
IEICE Transactions, 2014

On error modeling and analysis of approximate adders.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Recovery-based resilient latency-insensitive systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Kinematics of lower extremity for the young and elderly Chinese population during squatting.
Proceedings of the 7th International Conference on Biomedical Engineering and Informatics, 2014

2013
Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

SmipRef: An efficient method for multi-domain clock skew scheduling.
Integr., 2013

An efficient method for gradient-aware dummy fill synthesis.
Integr., 2013

Post-routing layer assignment for double patterning with timing critical paths consideration.
Integr., 2013

Layout decomposition with pairwise coloring for multiple patterning lithography.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Structural transformation for best-possible obfuscation of sequential circuits.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Retiming for Soft Error Minimization Under Error-Latching Window Constraints.
Proceedings of the Design, Automation and Test in Europe, 2013

Resource-constrained high-level datapath optimization in ASIP design.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Efficient design space exploration for component-based system design.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

An efficient algorithm for library-based cell-type selection in high-performance low-power designs.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Clock skew scheduling for timing speculation.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Optimal prescribed-domain clock skew scheduling.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Buffer minimization in pipelined SDF scheduling on multi-core platforms.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis.
IEEE Trans. VLSI Syst., 2011

A Special Section on Multicore Parallel CAD: Algorithm Design and Programming.
ACM Trans. Design Autom. Electr. Syst., 2011

MSV-Driven Floorplanning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Binning Optimization for Transparently-Latched Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Deprioritization of heavy users in wireless networks.
IEEE Communications Magazine, 2011

An efficient algorithm for multi-domain clock skew scheduling.
Proceedings of the Design, Automation and Test in Europe, 2011

Integrated circuit white space redistribution for temperature optimization.
Proceedings of the Design, Automation and Test in Europe, 2011

Optimal multi-domain clock skew scheduling.
Proceedings of the 48th Design Automation Conference, 2011

A practical method for multi-domain clock skew optimization.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Parallel cross-layer optimization of high-level synthesis and physical design.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Post-routing layer assignment for double patterning.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Low power discrete voltage assignment under clock skew scheduling.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Multicore Parallelization of Min-Cost Flow for CAD Applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Hybrid energy storage system integration for vehicles.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

iRetILP: an efficient incremental algorithm for min-period retiming under general delay model.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
A Timing-Dependent Power Estimation Framework Considering Coupling.
IEEE Trans. VLSI Syst., 2009

ACM Transactions on Design Automation of Electronic Systems (TODAES) special section call for papers: Parallel CAD: Algorithm design and programming.
ACM Trans. Design Autom. Electr. Syst., 2009

Gate Sizing by Lagrangian Relaxation Revisited.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Optimal Design of Gear Ratios and Offset for Energy Conservation of an Articulated Manipulator.
IEEE Trans. Automation Science and Engineering, 2009

An efficient current-based logic cell model for crosstalk delay analysis.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Binning optimization based on SSTA for transparently-latched circuits.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Retiming and resynthesis with sweep are complete for sequential transformation.
Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

Exception triggered DoS attacks on wireless networks.
Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009

Multicore parallel min-cost flow algorithm for CAD applications.
Proceedings of the 46th Design Automation Conference, 2009

Statistical reliability analysis under process variation and aging effects.
Proceedings of the 46th Design Automation Conference, 2009

Provably good and practically efficient algorithms for CMP dummy fill.
Proceedings of the 46th Design Automation Conference, 2009

Risk aversion min-period retiming under process variations.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Exploring adjacency in floorplanning.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Basic Data Structures.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Rectilinear Steiner Tree.
Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

Rectilinear Spanning Tree.
Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

Circuit Retiming: An Incremental Approach.
Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

Circuit Retiming.
Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

Fast Estimation of Timing Yield Bounds for Process Variations.
IEEE Trans. VLSI Syst., 2008

A new efficient retiming algorithm derived by formal manipulation.
ACM Trans. Design Autom. Electr. Syst., 2008

Optimizing wirelength and routability by searching alternative packings in floorplanning.
ACM Trans. Design Autom. Electr. Syst., 2008

EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Linear constraint graph for floorplan optimization with soft blocks.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

State space abstraction for parameterized self-stabilizing embedded systems.
Proceedings of the 8th ACM & IEEE International conference on Embedded software, 2008

An efficient incremental algorithm for min-area retiming.
Proceedings of the 45th Design Automation Conference, 2008

A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applications.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Advances in Computation of the Maximum of a Set of Gaussian Random Variables.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Unified Incremental Physical-Level and High-Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

An Effective Algorithm for Buffer Insertion in General Circuits Based on Network Flow.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Impact of Modern Process Technologies on the Electrical Parameters of Interconnects.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Timing budgeting under arbitrary process variations.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Address generation for nanowire decoders.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Design closure driven delay relaxation based on convex cost network flow.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Fast Min-Cost Buffer Insertion under Process Variations.
Proceedings of the 44th Design Automation Conference, 2007

Retiming for Synchronous Data Flow Graphs.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

New Block-Based Statistical Timing Analysis Approaches Without Moment Matching.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Fast Buffer Insertion for Yield Optimization Under Process Variations.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Statistical Timing Yield Optimization by Gate Sizing.
IEEE Trans. VLSI Syst., 2006

Clustering for Processing Rate Optimization.
IEEE Trans. VLSI Syst., 2006

Statistical Timing Analysis With Coupling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Gate-size optimization under timing constraints for coupling-noise reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Optimal wire retiming without binary search.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

An Efficient Data Structure for Maxplus Merge in Dynamic Programming.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Statistical timing verification for transparently latched circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Yield-Aware Cache Architectures.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Processing Rate Optimization by Sequential System Floorplanning.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Advances in Computation of the Maximum of a Set of Random Variables.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A revisit to floorplan optimization by Lagrangian relaxation.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Smart bit-width allocation for low power optimization in a systemc based ASIC design environment.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Optimal jumper insertion for antenna avoidance under ratio upper-bound.
Proceedings of the 43rd Design Automation Conference, 2006

An efficient retiming algorithm under setup and hold constraints.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Wire retiming as fixpoint computation.
IEEE Trans. VLSI Syst., 2005

Spanning graph-based nonrectilinear steiner tree algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Timing yield estimation using statistical static timing analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A unified framework for statistical timing analysis with coupling and multiple input switching.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Statistical gate sizing for timing yield optimization.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Trade-off between latch and flop for min-period sequential circuit designs with crosstalk.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Efficient algorithms for buffer insertion in general circuits based on network flow.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Leakage power optimization with dual-Vth library in high-level synthesis.
Proceedings of the 42nd Design Automation Conference, 2005

Incremental exploration of the combined physical and behavioral design space.
Proceedings of the 42nd Design Automation Conference, 2005

An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Deriving a new efficient algorithm for min-period retiming.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Interconnect estimation without packing via ACG floorplans.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Yield driven gate sizing for coupling-noise reduction under uncertainty.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Retiming for wire pipelining in system-on-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Efficient Steiner tree construction based on spanning graphs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Optimal gate sizing for coupling-noise reduction.
Proceedings of the 2004 International Symposium on Physical Design, 2004

ACG-Adjacent Constraint Graph for General Floorplans.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

A Flexible Data Structure for Efficient Buffer Insertion.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Clock schedule verification under process variations.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Timing macro-modeling of IP blocks with crosstalk.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Minimal period retiming under process variations.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Wire Retiming for System-on-Chip by Fixpoint Computation.
Proceedings of the 2004 Design, 2004

Efficient octilinear Steiner tree construction based on spanning graphs.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Timing analysis with crosstalk is a fixpoint on a complete lattice.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

BDD Based Procedures for a Theory of Equality with Uninterpreted Functions.
Formal Methods in System Design, 2003

Timing Verification with Crosstalk for Transparently Latched Circuits.
Proceedings of the 2003 Design, 2003

Interconnect-driven floorplanning by searching alternative packings.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Efficient minimum spanning tree construction without Delaunay triangulation.
Inf. Process. Lett., 2002

Clock schedule verification with crosstalk.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Track assignment: a desirable intermediate step between global routing and detailed routing.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001
Buffer minimization in pass transistor logic.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Timing Analysis with Crosstalk as Fixpoints on Complete Lattice.
Proceedings of the 38th Design Automation Conference, 2001

2000
Simultaneous routing and buffer insertion with restrictions onbuffer locations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Optimal low power X OR gate decomposition.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Global routing with crosstalk constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Sub-optimal Operating Time for Saving Energy of an Articulated Manipulator.
JRM, 1999

An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation.
Proceedings of the IEEE International Conference On Computer Design, 1999

Integrated floorplanning and interconnect planning.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Optimal river routing with crosstalk constraints.
ACM Trans. Design Autom. Electr. Syst., 1998

1997
Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

An exact gate decomposition algorithm for low-power technology mapping.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996
An optimal algorithm for river routing with crosstalk constraints.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Optimal non-uniform wire-sizing under the Elmore delay model.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996


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