Hao Yan

Orcid: 0000-0002-5312-4483

Affiliations:

Southeast University, National ASIC Center, Nanjing, China

According to our database¹, Hao Yan authored at least 21 papers between 2019 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

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Bibliography

2024

Fast and Accurate Aging-Aware Cell Timing Model via Graph Learning.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

2023

Aging-Aware Critical Path Selection via Graph Attention Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Optimized matrix ordering of sparse linear solver using a few-shot model for circuit simulation.

[BibT_eX]

[DOI]

Integr., November, 2023

CharTM: The dynamic stability characterization for memory based on tail distribution modeling.

[BibT_eX]

[DOI]

Microelectron. J., March, 2023

An efficient SRAM yield analysis method based on scaled-sigma adaptive importance sampling with meta-model accelerated.

[BibT_eX]

[DOI]

Integr., March, 2023

Topology-Aided Multicorner Timing Predictor for Wide Voltage Design.

[BibT_eX]

[DOI]

IEEE Des. Test, February, 2023

FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern Generator.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Fast and Accurate Wire Timing Estimation Based on Graph Learning.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A Novel Delay Calibration Method Considering Interaction between Cells and Wires.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Hardware Acceleration Linear Matrix Solvor Based on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2022

A Statistical Cell Delay Model for Estimating the 3σ Delay by Matching Kurtosis.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Quality Driven Systematic Approximation for Binary-Weight Neural Network Deployment.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021

An Adaptive Delay Model for Timing Yield Estimation under Wide-Voltage Range.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

An Efficient Adaptive Importance Sampling Method for SRAM and Analog Yield Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Non-Gaussian Adaptive Importance Sampling Method for High-Dimensional and Multi-Failure-Region Yield Analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019

Adaptive Clustering and Sampling for High-Dimensional and Multi-Failure-Region SRAM Yield Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2019 International Symposium on Physical Design, 2019

Efficient Yield Analysis for SRAM and Analog Circuits using Meta-Model based Importance Sampling Method.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Meta-Model based High-Dimensional Yield Analysis using Low-Rank Tensor Approximation.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Adaptive Low-Rank Tensor Approximation for SRAM Yield Analysis using Bootstrap Resampling.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Hao Yan

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