Nasim Farahini

According to our database1, Nasim Farahini authored at least 13 papers between 2013 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2017
SiLago-CoG: Coarse-Grained Grid-Based Design for Near Tape-Out Power Estimation Accuracy at High Level.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2015
Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAs.
ACM J. Emerg. Technol. Comput. Syst., 2015

Physical design aware system level synthesis of hardware.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Atomic stream computation unit based on micro-thread level parallelism.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric.
Microprocess. Microsystems, 2014

Customization methodology of a Coarse Grained Reconfigurable architecture.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Spiking brain models: Computation, memory and communication constraints for custom hardware implementation.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells.
Proceedings of the International Symposium on Quality Electronic Design, 2013

39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Global Control and Storage Synthesis for a System Level Synthesis Approach.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Distributed Runtime Computation of Constraints for Multiple Inner Loops.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

System level synthesis of hardware for DSP applications using pre-characterized function implementations.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013


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