Heng You

Orcid: 0000-0002-9386-8030

According to our database1, Heng You authored at least 28 papers between 2018 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
CCTD-MARL: Coupled Communication-Task Decoupling Framework for Multi-Agent Systems Under Partial Observability.
Big Data Cogn. Comput., 2026

An Approximate Digital Compute-In-Memory Macro with Reconfigurable Computational Precision for Neural Network Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
A Charge Domain SRAM Computing-in-Memory Macro With Quantized Interval-Optimized ADC and Input Bit-Level Sparsity-Optimized P2O-DAC for 8-b MAC Operation.
IEEE Trans. Very Large Scale Integr. Syst., May, 2025

An SRAM-based chunked computing-in-memory macro with a multi-slope voltage-time-digital converting ADC for efficient MAC operations.
IEICE Electron. Express, 2025

An energy-efficient readout method based on weight-flip-store coding and quantization cycle skipping technology for computing in memory.
IEICE Electron. Express, 2025

Dynamic Decision Correction Framework Integrating Path Optimization and Incomplete Information Handling.
Proceedings of the 2025 2nd International Conference on Generative Artificial Intelligence and Information Security, 2025

2024
A 1-8b Reconfigurable Digital SRAM Compute-in-Memory Macro for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

A Dual-Wordline 6T SRAM Computing-In-Memory Macro Featuring Full Signed Multi-Bit Computation for Lightweight Networks.
IEEE Access, 2024

A 409mV, Sub-10nW Power-on Reset Circuit Using Adaptive Accuracy Adjustment for Low Voltage Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A Transfer Approach Using Graph Neural Networks in Deep Reinforcement Learning.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023
Transfer Reinforcement Learning Based Negotiating Agent Framework.
Proceedings of the Advances in Knowledge Discovery and Data Mining, 2023

Transfer Learning based Agent for Automated Negotiation.
Proceedings of the 2023 International Conference on Autonomous Agents and Multiagent Systems, 2023

2022
A Low-Power High-Speed Sensing Scheme for Single-Ended SRAM.
IEICE Trans. Electron., November, 2022

An Accurate Low-Power Power-on-Reset Circuit in 55-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A fully integrated GaAs HBT power amplifier with enhanced efficiency for 5-GHz WLAN applications.
IEICE Electron. Express, 2022

A 0.6V 1.76nW power on reset circuit with high accuracy.
IEICE Electron. Express, 2022

Cross-domain adaptive transfer reinforcement learning based on state-action correspondence.
Proceedings of the Uncertainty in Artificial Intelligence, 2022

2021
Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Area-energy efficient CORDICs using new elementary-angle-set and base-2 exponent expansions scheme.
IEICE Electron. Express, 2021

A 8.83nW, 0.14ppm/℃ crystal oscillator using duty-cycling automatic amplitude control.
IEICE Electron. Express, 2021

A 0.5V 36nW 10-Transistor Power-on-Reset Circuit with High Accuracy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
An Energy-Efficient Level Shifter for Ultra Low-Voltage Digital LSIs.
IEEE Trans. Circuits Syst., 2020

A fast and low-power level shifter for multi-supply voltage designs.
IEICE Electron. Express, 2020

A 8bits, 6.2ps resolution two-step time-to-digital converter with set-reset-based arbiters and signal tracking mechanism.
IEICE Electron. Express, 2020

2019
A design method of CPR for wide voltage design.
IEICE Electron. Express, 2019

An ultra-low leakage energy efficient level shifter with wide conversion range.
IEICE Electron. Express, 2019

Design of low-power low-area asynchronous iterative multiplier.
IEICE Electron. Express, 2019

2018
A robust, subthreshold 12T SRAM bitcell with BL leakage compensation and bit-interleaving capability.
IEICE Electron. Express, 2018


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