Yong Hei

Orcid: 0000-0002-8025-2739

According to our database1, Yong Hei authored at least 27 papers between 2010 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
An Energy-Efficient Level Shifter for Ultra Low-Voltage Digital LSIs.
IEEE Trans. Circuits Syst., 2020

Erratum: A low-overhead error detection and correction technique with a relaxed error timing constraint for variation-tolerance [IEICE Electronics Express Vol. 16 (2019) No. 14 pp. 20190342].
IEICE Electron. Express, 2020

Erratum: Snake: An asynchronous pipeline for ultra-low-power applications [IEICE Electronics Express Vol. 16 (2019) No. 12 pp. 20190293].
IEICE Electron. Express, 2020

2019
A Modified Signal Flow Graph and Corresponding Conflict-Free Strategy for Memory-Based FFT Processor Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A low-overhead error detection and correction technique with a relaxed error timing constraint for variation-tolerance.
IEICE Electron. Express, 2019

Snake: An asynchronous pipeline for ultra-low-power applications.
IEICE Electron. Express, 2019

A design method of CPR for wide voltage design.
IEICE Electron. Express, 2019

An ultra-low leakage energy efficient level shifter with wide conversion range.
IEICE Electron. Express, 2019

Design of low-power low-area asynchronous iterative multiplier.
IEICE Electron. Express, 2019

2018
A practical, low-overhead, one-cycle correction design method for variation-tolerant digital circuits.
IEICE Electron. Express, 2018

An anti-alias harmonic-reject phase modulation for digital outphasing transmitter.
IEICE Electron. Express, 2018

A low power and glitch-free circular rotation phase modulator for outphasing transmitter.
IEICE Electron. Express, 2018

Click-Based Asynchronous Mesh Network with Bounded Bundled Data.
Proceedings of the 47th International Conference on Parallel Processing, 2018

2017
A Low-Voltage SRAM Sense Amplifier With Offset Cancelling Using Digitized Multiple Body Biasing.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

An improved phase digitization mechanism for fast-locking low-power all-digital PLLs.
IEICE Electron. Express, 2017

Erratum: A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes [IEICE Electronics Express Vol. 14 (2017) No. 15 pp. 20170660].
IEICE Electron. Express, 2017

A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes.
IEICE Electron. Express, 2017

A PMOS read-port 8T SRAM cell with optimized leakage power and enhanced performance.
IEICE Electron. Express, 2017

How to think about self-timed systems.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
A 1V, 1.1mW mixed-signal hearing aid SoC in 0.13μm CMOS process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A 1-V, 1.2-mA fully integrated SoC for digital hearing aids.
Microelectron. J., 2015

A Low Power, High Performance Analog Front-End Circuit for 1 V Digital Hearing Aid SoC.
Circuits Syst. Signal Process., 2015

A low voltage SRAM sense amplifier with offset cancelling using digitized multiple body biasing.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A design of subthreshold SRAM cell based on RSCE and RNCE.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2011
A novel channel estimation algorithm in OFDM power line communication system.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
A Parallel-Layered Belief-Propagation Decoder for Non-layered LDPC Codes.
J. Commun., 2010

New Trends in Microprocessor Architecture for Parallel Computing.
Proceedings of the Fifth International Conference on Frontier of Computer Science and Technology, 2010


  Loading...