Henrique Cota de Freitas

According to our database1, Henrique Cota de Freitas authored at least 36 papers between 2001 and 2020.

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Bibliography

2020
Reconfigurable FPGA-Based K-Means/K-Modes Architecture for Network Intrusion Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Hybrid Approach based on SARIMA and Artificial Neural Networks for Knowledge Discovery Applied to Crime Rates Prediction.
Proceedings of the 22nd International Conference on Enterprise Information Systems, 2020

2019
A Fast Parallel K-Modes Algorithm for Clustering Nucleotide Sequences to Predict Translation Initiation Sites.
J. Comput. Biol., 2019

A comprehensive performance evaluation of the BinLPT workload-aware loop scheduler.
Concurr. Comput. Pract. Exp., 2019

On the Performance and Isolation of Asymmetric Microkernel Design for Lightweight Manycores.
Proceedings of the IX Brazilian Symposium on Computing Systems Engineering, 2019

2018
Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

Design Space Exploration of Energy Efficient NoC-and Cache-Based Many-Core Architecture.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

2017
Scalable spatio-temporal parallel parameterizable stream-based JPEG-LS encoder.
IEICE Electron. Express, 2017

CAP Bench: a benchmark suite for performance and energy evaluation of low-power many-core processors.
Concurr. Comput. Pract. Exp., 2017

Design methodology for workload-aware loop scheduling strategies based on genetic algorithm and simulation.
Concurr. Comput. Pract. Exp., 2017

Using the Nanvix Operating System in Undergraduate Operating System Courses.
Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017

Energy Consumption Improvement of Shared-Cache Multicore Clusters Based on Explicit Simultaneous Multithreading.
Proceedings of the 2017 International Symposium on Computer Architecture and High Performance Computing Workshops, 2017

Assessing the Performance of the SRR Loop Scheduler with Irregular Workloads.
Proceedings of the International Conference on Computational Science, 2017

2016
Parallelization of the next Closure algorithm for generating the minimum set of implication rules.
Artif. Intell. Res., 2016

A Low-Cost Energy-Efficient Raspberry Pi Cluster for Data Mining Algorithms.
Proceedings of the Euro-Par 2016: Parallel Processing Workshops, 2016

2015
On the energy efficiency and performance of irregular application executions on multicore, NUMA and manycore platforms.
J. Parallel Distributed Comput., 2015

Performance evaluation of single- and multi-hop wireless networks-on-chip with NAS Parallel Benchmarks.
J. Braz. Comput. Soc., 2015

2013
Method for teaching parallelism on heterogeneous many-core processors using research projects.
Proceedings of the IEEE Frontiers in Education Conference, 2013

2012
Parallel and distributed kmeans to identify the translation initiation site of proteins.
Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics, 2012

Introducing parallel programming to traditional undergraduate courses.
Proceedings of the IEEE Frontiers in Education Conference, 2012

2011
High Latency and Contention on Shared L2-Cache for Many-Core Architectures.
Parallel Process. Lett., 2011

Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment.
Int. J. Reconfigurable Comput., 2011

2010
Parallel Shared-Memory Workloads Performance on Asymmetric Multi-core Architectures.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

Impact of Parallel Workloads on NoC Architecture Design.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

TLP and ILP exploitation through a reconfigurable multiprocessor system.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

A Distributed Algorithm for Formal Concepts Processing based on Search Subspaces.
Proceedings of the ICEIS 2010 - Proceedings of the 12th International Conference on Enterprise Information Systems, Volume 1, DISI, Funchal, Madeira, Portugal, June 8, 2010

2009
Programmable multi-cluster noc architecture to support collective communication patterns.
PhD thesis, 2009

Performance Evaluation of NoC Architectures for Parallel Workloads.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Design of Interleaved Multithreading for Network Processors on Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008
NOC architecture design for multi-cluster chips.
Proceedings of the FPL 2008, 2008

A High-Throughput Multi-cluster NoC Architecture.
Proceedings of the 11th IEEE International Conference on Computational Science and Engineering, 2008

2007
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Reconfigurable crossbar switch architecture for network processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2003
Didactic architectures and simulator for network processor learning.
Proceedings of the 2003 workshop on Computer architecture education, 2003

2001
Information Systems Planning: Contributions from Organizational Learning.
Proceedings of the ICEIS 2001, 2001


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