Antonio Carlos Schneider Beck
Orcid: 0000-0002-4492-1747Affiliations:
- Universidade Federal do Rio Grande do Sul
According to our database1,
Antonio Carlos Schneider Beck
authored at least 176 papers
between 2003 and 2024.
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on orcid.org
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on inf.ufrgs.br
On csauthors.net:
Bibliography
2024
IEEE Trans. Parallel Distributed Syst., March, 2024
2023
Multiprovision: a Design Space Exploration tool for multi-tenant resource provisioning in CPU-GPU environments.
Des. Autom. Embed. Syst., December, 2023
MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems.
Integr., November, 2023
Energy-aware fully-adaptive resource provisioning in collaborative CPU-FPGA cloud environments.
J. Parallel Distributed Comput., June, 2023
Using evolutionary metaheuristics to solve the mapping and routing problem in networks on chip.
Des. Autom. Embed. Syst., June, 2023
Concurr. Comput. Pract. Exp., 2023
Mitigating execution unit contention in parallel applications using instruction-aware mapping.
Concurr. Comput. Pract. Exp., 2023
Improving the efficiency of graph algorithm executions on high-performance computing.
Concurr. Comput. Pract. Exp., 2023
Proceedings of the XIII Brazilian Symposium on Computing Systems Engineering, 2023
Proceedings of the XIII Brazilian Symposium on Computing Systems Engineering, 2023
Proceedings of the 31st Euromicro International Conference on Parallel, 2023
Dynamic Offloading for Improved Performance and Energy Efficiency in Heterogeneous IoT-Edge-Cloud Continuum.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Resource Provisioning for CPU-FPGA Environments with Adaptive HLS-Versioning and DVFS.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design and Architecture for Signal and Image Processing, 2023
Proceedings of the Advanced Information Networking and Applications, 2023
2022
Optimizing the EDP of OpenMP applications via concurrency throttling and frequency boosting.
J. Syst. Archit., 2022
ERIN: Energy-Aware Resource-Provisioning Framework for CPU-FPGA Multitenant Environment.
IEEE Des. Test, 2022
An energy efficient multi-target binary translator for instruction and data level parallelism exploitation.
Des. Autom. Embed. Syst., 2022
Thermal-Aware Thread and Turbo Frequency Throttling Optimization for Parallel Applications.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022
On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022
ConfAx: Exploiting Approximate Computing for Configurable FPGA CNN Acceleration at the Edge.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
A Runtime and Non-Intrusive Approach to Optimize EDP by Tuning Threads and CPU Frequency for OpenMP Applications.
IEEE Trans. Parallel Distributed Syst., 2021
Synergistically Exploiting CNN Pruning and HLS Versioning for Adaptive Inference on Multi-FPGAs at the Edge.
ACM Trans. Embed. Comput. Syst., 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Computers, 2021
J. Syst. Archit., 2021
J. Parallel Distributed Comput., 2021
J. Parallel Distributed Comput., 2021
Enabling Near-Data Accelerators Adoption by Through Investigation of Datapath Solutions.
Int. J. Parallel Program., 2021
Des. Autom. Embed. Syst., 2021
TRIPP: Transparent Resource Provisioning for Multi-Tenant CPU-GPU based Cloud Environments.
Proceedings of the XI Brazilian Symposium on Computing Systems Engineering, 2021
Proceedings of the XI Brazilian Symposium on Computing Systems Engineering, 2021
ETCF - Energy-Aware CPU Thread Throttling and Workload Balancing Framework for CPU-FPGA Collaborative Environments.
Proceedings of the XI Brazilian Symposium on Computing Systems Engineering, 2021
FAIR: Fully-Adaptive Framework for Improving Resource Provisioning in Collaborative CPU-FPGA Cloud Environments.
Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021
Proceedings of the 29th Euromicro International Conference on Parallel, 2021
Optimizing Parallel Applications via Dynamic Concurrency Throttling and Turbo Boosting.
Proceedings of the 29th Euromicro International Conference on Parallel, 2021
Combining Thread Throttling and Mapping to Optimize the EDP of Parallel Applications.
Proceedings of the 29th Euromicro International Conference on Parallel, 2021
EDP Optimization of Parallel Applications via CPU Frequency Scaling on AMD Processors.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Proceedings of the X Brazilian Symposium on Computing Systems Engineering, 2020
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020
Unlocking the Full Potential of Heterogeneous Accelerators by Using a Hybrid Multi-Target Binary Translator.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020
Maximizing Throughput-per-Joule of a Hybrid Communication Infrastructure Through a Software-Hardware based DVFS Mechanism.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020
Decreasing the Learning Cost of Offline Parallel Application Optimization Strategies.
Proceedings of the 28th Euromicro International Conference on Parallel, 2020
A Reliability-Oriented Machine Learning Strategy for Heterogeneous Multicore Application Mapping.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 22nd IEEE International Conference on High Performance Computing and Communications; 18th IEEE International Conference on Smart City; 6th IEEE International Conference on Data Science and Systems, 2020
An Application-Driven Approach to Mitigate Aging by Tuning the TLP and Allocation Strategies.
Proceedings of the 22nd IEEE International Conference on High Performance Computing and Communications; 18th IEEE International Conference on Smart City; 6th IEEE International Conference on Data Science and Systems, 2020
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
A Machine Learning Approach for Reliability-Aware Application Mapping for Heterogeneous Multicores.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Enhancing Thread-Level Parallelism in Asymmetric Multicores using Transparent Instruction Offloading.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Parallel Computing Hits the Power Wall - Principles, Challenges, and a Survey of Solutions
Springer Briefs in Computer Science, Springer, ISBN: 978-3-030-28718-4, 2019
IEEE Trans. Parallel Distributed Syst., 2019
A Technologically Agnostic Framework for Cyber-Physical and IoT Processing-in-Memory-based Systems Simulation.
Microprocess. Microsystems, 2019
Predicting performance in multi-core systems with shared reconfigurable accelerators.
J. Syst. Archit., 2019
A fast and accurate hybrid fault injection platform for transient and permanent faults.
Des. Autom. Embed. Syst., 2019
A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
The Impact of Turbo Frequency on the Energy, Performance, and Aging of Parallel Applications.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
On the influence of Data Migration in Dynamic Thread Management of Parallel Applications.
Proceedings of the IX Brazilian Symposium on Computing Systems Engineering, 2019
Proceedings of the IX Brazilian Symposium on Computing Systems Engineering, 2019
Proceedings of the 31st International Symposium on Computer Architecture and High Performance Computing, 2019
Proceedings of the 31st International Symposium on Computer Architecture and High Performance Computing, 2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019
Machine Learning-Based Processor Adaptability Targeting Energy, Performance, and Reliability.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
The Impact of Parallel Programming Interfaces on the Aging of a Multicore Embedded Processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Improving Software-based Techniques for Soft Error Mitigation in OoO Superscalar Processors.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
A New Hardware Friendly 2D-DCT HEVC Compliant Algorithm and its High Throughput and Low Power Hardware Design.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
TransRec: Improving Adaptability in Single-ISA Heterogeneous Systems with Transparent and Reconfigurable Acceleration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Exploiting Reconfigurable Vector Processing for Energy-Efficient Computation in 3D-Stacked Memories.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019
2018
Dynamic Trade-off among Fault Tolerance, Energy Consumption, and Performance on a Multiple-Issue VLIW Processor.
IEEE Trans. Multi Scale Comput. Syst., 2018
Sci. Comput. Program., 2018
Microprocess. Microsystems, 2018
Automatic Tuning TLP and DVFS for EDP with a Non-intrusive Genetic Algorithm Framework.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Approximate on-the-fly coarse-grained reconfigurable acceleration for general-purpose applications.
Proceedings of the 55th Annual Design Automation Conference, 2018
Adaptive and polymorphic VLIW processor to optimize fault tolerance, energy consumption, and performance.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
2017
Special issue with selected papers from 2016 Brazilian Symposium on Computer Engineering (SBESC 2016).
Des. Autom. Embed. Syst., 2017
Potential Gains in EDP by Dynamically Adapting the Number of Threads for OpenMP Applications in Embedded Systems.
Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017
Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017
A framework to automatically generate heterogeneous organization reconfigurable multiprocessing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Improving EDP in multi-core embedded systems through multidimensional frequency scaling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
A Mechanism for energy-efficient reuse of decoding and scheduling of x86 instruction streams.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Investigating different general-purpose and embedded multicores to achieve optimal trade-offs between performance and energy.
J. Parallel Distributed Comput., 2016
Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors.
ACM J. Emerg. Technol. Comput. Syst., 2016
Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism.
Des. Autom. Embed. Syst., 2016
The Potential of Accelerating Image-Processing Applications by Using Approximate Function Reuse.
Proceedings of the VI Brazilian Symposium on Computing Systems Engineering, 2016
How Programming Languages and Paradigms Affect Performance and Energy in Multithreaded Applications.
Proceedings of the VI Brazilian Symposium on Computing Systems Engineering, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016
2015
Performance and Energy Evaluation of Different Multi-Threading Interfaces in Embedded and General Purpose Systems.
J. Signal Process. Syst., 2015
Adaptive and dynamic reconfigurable multiprocessor system to improve software productivity.
IET Comput. Digit. Tech., 2015
Evaluation of energy savings on a VLIW processor through dynamic issue-width adaptation.
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Optimized Use of Parallel Programming Interfaces in Multithreaded Embedded Architectures.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 39th IEEE Annual Computer Software and Applications Conference, 2015
Proceedings of the 39th IEEE Annual Computer Software and Applications Conference, 2015
2014
Proceedings of the 2014 Brazilian Symposium on Computing Systems Engineering, 2014
Proceedings of the 2014 Brazilian Symposium on Computing Systems Engineering, 2014
Proceedings of the 2014 Brazilian Symposium on Computing Systems Engineering, 2014
Potential of Using a Reconfigurable System on a Superscalar Core for ILP Improvements.
Proceedings of the 2014 Brazilian Symposium on Computing Systems Engineering, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
Proceedings of the III Brazilian Symposium on Computing Systems Engineering, 2013
Proceedings of the III Brazilian Symposium on Computing Systems Engineering, 2013
Proceedings of the III Brazilian Symposium on Computing Systems Engineering, 2013
Proceedings of the III Brazilian Symposium on Computing Systems Engineering, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A transparent and energy aware reconfigurable multiprocessor platform for simultaneous ILP and TLP exploitation.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Mixing static and dynamic strategies for high performance and low area reconfigurable systems.
Int. J. High Perform. Syst. Archit., 2012
2011
Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment.
Int. J. Reconfigurable Comput., 2011
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
2010
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
Dynamic Reconfigurable Architectures and Transparent Optimization Techniques - Automatic Acceleration of Software Execution.
Springer, ISBN: 978-90-481-3912-5, 2010
2009
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
Proceedings of the Reconfigurable Computing: Architectures, 2009
2008
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Reducing interconnection cost in coarse-grained dynamic computing through multistage network.
Proceedings of the FPL 2008, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Reconfigurable Computing: Architectures, 2008
2007
Reconfigurable Acceleration with Binary Compatibility for General Purpose Processors.
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007
Transparent acceleration of data dependent instructions for general purpose processors.
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
2006
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Advantages of Java Processors in Cache Performance and Power for Embedded Applications.
Proceedings of the Embedded Computer Systems: Architectures, 2006
Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006
2005
Trading Time and Space on Low Power Embedded Architectures with Dynamic Instruction Merging.
J. Low Power Electron., 2005
Exploiting Java through binary translation for low power embedded reconfigurable systems.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the New Trends and Technologies in Computer-Aided Learning for Computer-Aided Design, 2005
Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility.
Proceedings of the 42nd Design Automation Conference, 2005
2004
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications.
Proceedings of the Computer Systems: Architectures, 2004
2003
Proceedings of the VLSI-SOC: From Systems to Chips, 2003
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003