Tatiana Gadelha Serra dos Santos

According to our database1, Tatiana Gadelha Serra dos Santos authored at least 10 papers between 2000 and 2009.

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Bibliography

2009
FPGA implementation and performance evaluation of an RFC 2544 compliant Ethernet test set.
Int. J. High Perform. Syst. Archit., 2009

2008
NOC architecture design for multi-cluster chips.
Proceedings of the FPL 2008, 2008

2007
High Level RTOS Scheduler Modeling for a Fast Design Validation.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2006
Scheduling refinement in abstract RTOS models.
ACM Trans. Embed. Comput. Syst., 2006

FPGA Design of A H.264/AVC Main Profile Decoder for HDTV.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Reusing Traces in a Dynamic Conditional Execution Architecture.
Proceedings of the 17th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2005), 2005

2004
Reusing values in a dynamic conditional execution architecture.
PhD thesis, 2004

2003
Complex Branch Profiling for Dynamic Conditional Execution.
Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2003), 2003

2001
Evaluating the Effects of Branch Prediction Accuracy on the Performance of SMT Architectures.
Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001

2000
Analyzing Instruction Prefetch Schemes in Superscalar Architectures.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000


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