Mateus B. Rutzig

According to our database1, Mateus B. Rutzig authored at least 39 papers between 2006 and 2019.

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Bibliography

2019
Boosting SIMD Benefits through a Run-time and Energy Efficient DLP Detection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Semi-Autonomous Navigation for Virtual Tactical Simulations in the Military Domain.
Proceedings of 8th International Conference on Simulation and Modeling Methodologies, 2018

Runtime Vectorization of Conditional Code and Dynamic Range Loops to ARM NEON Engine.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

HyHeMPS: A Hybrid Communication Infrastructure for MPSoCs.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

Improving Software Productivity and Performance Through a Transparent SIMD Execution.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
A framework to automatically generate heterogeneous organization reconfigurable multiprocessing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Improving EDP in multi-core embedded systems through multidimensional frequency scaling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
The Impact of Heterogeneity on a Reconfigurable Multicore System.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A reconfigurable heterogeneous multicore with a homogeneous ISA.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Evaluating Schedulers in a Reconfigurable Multicore Heterogeneous System.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015
Adaptive and dynamic reconfigurable multiprocessor system to improve software productivity.
IET Computers & Digital Techniques, 2015

Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
A transparent and adaptive reconfigurable system.
Microprocessors and Microsystems - Embedded Hardware Design, 2014

Towards a Dynamic and Reconfigurable Multicore Heterogeneous System.
Proceedings of the 2014 Brazilian Symposium on Computing Systems Engineering, 2014

2013
Multicore Systems on Chip.
, 2013

Towards a multiple-ISA embedded system.
Journal of Systems Architecture - Embedded Systems Design, 2013

A run-time adaptive multiprocessor system.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A transparent and energy aware reconfigurable multiprocessor platform for simultaneous ILP and TLP exploitation.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Mixing static and dynamic strategies for high performance and low area reconfigurable systems.
IJHPSA, 2012

Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

2011
Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment.
Int. J. Reconfig. Comp., 2011

A reconfigurable fabric supporting full C/C++ input.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

CReAMS: An Embedded Multiprocessor Platform.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

Towards an Adaptable Multiple-ISA Reconfigurable Processor.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
TLP and ILP exploitation through a reconfigurable multiprocessor system.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

A low-energy approach for context memory in reconfigurable systems.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Multi-core Systems on Chip.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
A low cost and adaptable routing network for reconfigurable systems.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Dynamically Adapted Low Power ASIPs.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Binary translation process to optimize nanowire arrays usage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Balancing reconfigurable data path resources according to application requirements.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Reducing interconnection cost in coarse-grained dynamic computing through multistage network.
Proceedings of the FPL 2008, 2008

Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications.
Proceedings of the Design, Automation and Test in Europe, 2008

Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Transparent Dataflow Execution for Embedded Applications.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2006
Cache performance impacts for stack machines in embedded systems.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Advantages of Java Processors in Cache Performance and Power for Embedded Applications.
Proceedings of the Embedded Computer Systems: Architectures, 2006


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