Lech Józwiak
Affiliations:- Eindhoven University of Technology, Netherlands
According to our database1,
Lech Józwiak
authored at least 130 papers
between 1990 and 2023.
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Bibliography
2023
Microprocess. Microsystems, April, 2023
2021
Quality-driven Design of Deep Neural Network Accelerators for CPS and IoT Applications.
Proceedings of the 10th Mediterranean Conference on Embedded Computing, 2021
2018
An Access-Pattern-Aware On-Chip Vector Memory System with Automatic Loading for SIMD Architectures.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018
2017
Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project.
Microprocess. Microsystems, 2017
2016
Microprocess. Microsystems, 2016
Proceedings of the 5th Mediterranean Conference on Embedded Computing, 2016
Proceedings of the 5th Mediterranean Conference on Embedded Computing, 2016
2015
Microprocess. Microsystems, 2015
Proceedings of the 4th Mediterranean Conference on Embedded Computing, 2015
Proceedings of the 9th International Conference on Signal Processing and Communication Systems, 2015
Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015
2014
Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding.
Microprocess. Microsystems, 2014
Microprocess. Microsystems, 2014
Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014
Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014
Automatic complex instruction identification for efficient application mapping onto ASIPs.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
Proceedings of the 12th IEEE International Conference on Industrial Informatics, 2014
BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
2013
Parallel processing of intersections for ray-tracing in application-specific processors and GPGPUs.
Microprocess. Microsystems, 2013
Microprocess. Microsystems, 2013
Application-specific processors and system-on-chips for embedded and pervasive applications.
Microprocess. Microsystems, 2013
Microprocess. Microsystems, 2013
Design of massively parallel hardware multi-processors for highly-demanding embedded applications.
Microprocess. Microsystems, 2013
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013
Quality-driven model-based design of multi-processor embedded systems for highlydemanding applications.
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013
Proceedings of the Tenth International Conference on Information Technology: New Generations, 2013
HW/SW architecture co-synthesis of ASIP-based MPSoCs for highly- demanding applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
A Reconfigurable Ray-Tracing Multi-Processor SoC with Hardware Replication-Aware Instruction Set Extension.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2013
An Efficient Method for Energy Estimation of Application Specific Instruction-Set Processors.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013
2012
Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors.
VLSI Design, 2012
Scalable communication architectures for massively parallel hardware multi-processors.
J. Parallel Distributed Comput., 2012
Proceedings of the High Performance Computing for Computational Science, 2012
Design space exploration in application-specific hardware synthesis for multiple communicating nested loops.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
Advanced Architectures for Highly-demanding Embedded and Pervasive Applications.
Proceedings of the PECCS 2011, 2011
Issues and Challenges in Development of Massively-Parallel Heterogeneous MPSoCs Based on Adaptable ASIPs.
Proceedings of the 19th International Euromicro Conference on Parallel, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the Algorithms and Architectures for Parallel Processing, 2011
A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
2010
Integr., 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the Seventh International Conference on Information Technology: New Generations, 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
2009
J. Circuits Syst. Comput., 2009
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey.
Proceedings of the Embedded Computer Systems: Architectures, 2009
Proceedings of the Reconfigurable Computing: Architectures, 2009
2008
J. Syst. Archit., 2008
Proceedings of the Fifth International Conference on Information Technology: New Generations (ITNG 2008), 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
2006
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006
Proceedings of the Architecture of Computing Systems, 2006
2005
J. Syst. Archit., 2005
J. Syst. Archit., 2005
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
High-quality Sub-function Construction in the Information-driven Circuit Synthesis with Gates.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
2004
General decomposition of incompletely specified sequential machines with multi-state behavior realization.
J. Syst. Archit., 2004
An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment Methods.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004
2003
J. Syst. Archit., 2003
J. Syst. Archit., 2003
Artif. Intell. Rev., 2003
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
2002
Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits.
VLSI Design, 2002
Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture.
IEEE Micro, 2002
IEEE Micro, 2002
Genetic engineering versus natural evolution: Genetic algorithms with deterministic operators.
J. Syst. Archit., 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
2001
Functional decomposition with an efficient input support selection for sub-functions based on information relationship measures.
J. Syst. Archit., 2001
J. Syst. Archit., 2001
J. Syst. Archit., 2001
High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001
Fast and Compact Sequential Circuits through the Information-Driven Circuit Synthesis.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001
Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001
High-quality sub-function construction in functional decomposition based on information relationship measures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
Proceedings of the 26th EUROMICRO 2000 Conference, 2000
1999
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999
Technology Driven Multilevel Logic Synthesis Based on Functional Decomposition into Gates.
Proceedings of the 25th EUROMICRO '99 Conference, 1999
Efficient Input Support Selection for Sub-functions in Functional Decomposition Based on Information Relationship Measures.
Proceedings of the 25th EUROMICRO '99 Conference, 1999
The Influence of the Number of Values in Sub-Functions on the Effectiveness and Efficiency of the Functional Decomposition.
Proceedings of the 25th EUROMICRO '99 Conference, 1999
Learning in Hardware: Architecture and Implementation of an FPGA-Based Rough Set Machine.
Proceedings of the 25th EUROMICRO '99 Conference, 1999
Functional Decomposition based on Information Relationship Measures Extremely Effective and Efficient for Symmetric Functions.
Proceedings of the 25th EUROMICRO '99 Conference, 1999
Proceedings of the 25th EUROMICRO '99 Conference, 1999
Synthesis of XOR Storage Schemes with Different Cost for Minimization of Memory Contention.
Proceedings of the 25th EUROMICRO '99 Conference, 1999
1998
Application of the Information Measures to Input Support Selection in Functional Decomposition.
Proceedings of the Rough Sets and Current Trends in Computing, 1998
Analysis and Synthesis of Information Systems with Information Relationships and Measures.
Proceedings of the Rough Sets and Current Trends in Computing, 1998
Efficient Logic Synthesis for FPGAs with Functional Decomposition Based on Information Relationship Measure.
Proceedings of the 24th EUROMICRO '98 Conference, 1998
Proceedings of the 24th EUROMICRO '98 Conference, 1998
Proceedings of the 24th EUROMICRO '98 Conference, 1998
Proceedings of the 24th EUROMICRO '98 Conference, 1998
An Efficient Approach to Decomposition of Multi-Output Boolean Functions with Large Sets of Bound Variables.
Proceedings of the 24th EUROMICRO '98 Conference, 1998
1997
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997
Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations.
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997
Interactive codesign for real-time embedded control systems: task graph generation from SA/VHDL models.
Proceedings of the 23rd EUROMICRO Conference '97, 1997
Fast Minimization Of Multi-Output Boolean Functions In Sum-Of-Condition-Decoders Structures.
Proceedings of the 23rd EUROMICRO Conference '97, 1997
Proceedings of the 23rd EUROMICRO Conference '97, 1997
Information Relationships and Measures An Analysis Apparatus for Efficient Information System Synthesis.
Proceedings of the 23rd EUROMICRO Conference '97, 1997
1996
Proceedings of the 22rd EUROMICRO Conference '96, 1996
1995
VLSI Design, 1995
Efficient decomposition of assigned sequential machines and Boolean functions for PLD implementations.
Proceedings of the Electronic Technology Directions to the Year 2000, 1995
1993
1992
J. Circuits Syst. Comput., 1992
1991
Microprocessing and Microprogramming, 1991
1990
Microprocessing and Microprogramming, 1990
Proceedings of the European Design Automation Conference, 1990