Hideki Ando

According to our database, Hideki Ando authored at least 35 papers between 1988 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Localizing the Tag Comparisons in the Wakeup Logic to Reduce Energy Consumption of the Issue Queue.

Kenichiro Mori, Sota Kosugi, Hiroto Yoshida, Hajime Shimada, Hideki Ando

Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

2022

Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison.

Yasutaka Matsuda, Ryota Shioya, Hideki Ando

IEICE Trans. Inf. Syst., 2022

Segmenting Age Matrices to Improve Instruction Scheduling without Increasing Delay and Area.

Hideki Ando

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2019

Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline.

Reoma Matsuo, Ryota Shioya, Hideki Ando

IEEE Comput. Archit. Lett., 2019

SWQUE: A Mode Switching Issue Queue with Priority-Correcting Circular Queue.

Hideki Ando

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

2018

Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications.

Keita Doi, Ryota Shioya, Hideki Ando

J. Inf. Process., 2018

Performance Improvement by Prioritizing the Issue of the Instructions in Unconfident Branch Slices.

Hideki Ando

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Rearranging Random Issue Queue with High IPC and Short Delay.

Shinji Sakai, Taishi Suenaga, Ryota Shioya, Hideki Ando

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode.

Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, Hideki Ando

Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2016

FXA: Executing Instructions in Front-End for Energy Efficiency.

Ryota Shioya, Ryo Takami, Masahiro Goshima, Hideki Ando

IEICE Trans. Inf. Syst., 2016

Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency.

Ryota Shioya, Hideki Ando

IEICE Trans. Inf. Syst., 2016

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control.

Hideki Ando, Ryota Shioya

IEICE Trans. Inf. Syst., 2016

2014

MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism.

Yuya Kora, Kyohei Yamaguchi, Hideki Ando

IEICE Trans. Inf. Syst., 2014

A Front-End Execution Architecture for High Energy Efficiency.

Ryota Shioya, Masahiro Goshima, Hideki Ando

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Energy efficiency improvement of renamed trace cache through the reduction of dependent path length.

Ryota Shioya, Hideki Ando

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP.

Yuya Kora, Kyohei Yamaguchi, Hideki Ando

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012

Delay Evaluation of Issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path Identification.

Kyohei Yamaguchi, Yuya Kora, Hideki Ando

IEICE Trans. Inf. Syst., 2012

2011

Evaluation of issue queue delay: Banking tag RAM and identifying correct critical path.

Kyohei Yamaguchi, Yuya Kora, Hideki Ando

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010

Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction.

Yusuke Tanaka, Hideki Ando

IEICE Trans. Inf. Syst., 2010

2009

Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation.

Kazunaga Hyodo, Kengo Iwamoto, Hideki Ando

IEICE Trans. Inf. Syst., 2009

Reducing register file size through instruction pre-execution enhanced by value prediction.

Yusuke Tanaka, Hideki Ando

Proceedings of the 27th International Conference on Computer Design, 2009

2008

Two-Step Physical Register Deallocation for Data Prefetching and Address Pre-Calculation.

Akihiro Yamamoto, Yusuke Tanaka, Hideki Ando, Toshio Shimada

Inf. Media Technol., 2008

2007

Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation.

Akihiro Yamamoto, Yusuke Tanaka, Hideki Ando, Toshio Shimada

Proceedings of the 2007 workshop on MEmory performance, 2007

2006

Limits of Thread-Level Parallelism in Non-numerical Programs.

Akio Nakajima, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada

Inf. Media Technol., 2006

2003

Pipeline stage unification: a low-energy consumption technique for future mobile processors.

Hajime Shimada, Hideki Ando, Toshio Shimada

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2002

A preactivating mechanism for a VT-CMOS cache using address prediction.

Ryo Fujioka, Kiyokazu Katayama, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

1999

Distributed memoryless point convergence algorithm for mobile robots with limited visibility.

Hideki Ando, Yoshinobu Oasa, Ichiro Suzuki, Masafumi Yamashita

IEEE Trans. Robotics Autom., 1999

An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism.

Ryotaro Kobayashi, Yukihiro Ogawa, Hideki Ando, Toshio Shimada, Mitsuaki Iwata

Proceedings of the 25th EUROMICRO '99 Conference, 1999

1998

Software pipelining with path selection.

Chikako Nakanishi, Hideki Ando, Tetsuya Hara, Masao Nakaya

Syst. Comput. Jpn., 1998

1996

Performance Comparison of ILP Machines with Cycle Time Evaluation.

Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya

Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996

1995

Code scheduling on a superscalar processor: SARCH.

Chikako Nakanishi, Hideki Ando, Hirohisa Machida, Masao Nakaya

Syst. Comput. Jpn., 1995

Unconstrained Speculative Execution with Predicated State Buffering.

Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya

Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

1993

A VLSI chip set for a large-scale parallel inference machine: PIM/m.

Hirohisa Machida, Hideki Ando, Kenichi Yasuda, Kiyohiro Furutani, Yukihiro Yamashita, Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Masayoshi Sakao, Masao Nakaya

IEEE J. Solid State Circuits, March, 1993

Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine.

Hideki Ando, Chikako Nakanishi, Hirohisa Machida, Tetsuya Hara, Satoru Kishida, Masao Nakaya

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1988

A DSP line equalizer VLSI for TCM digital subscriber-line transmission.

Hideki Ando, Masao Nakaya, Hiroki Hona, Ihuo Iizuka, Yasutaka Horiba

IEEE J. Solid State Circuits, February, 1988